Patents by Inventor Ryan KEECH
Ryan KEECH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170484Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.Type: ApplicationFiled: January 29, 2024Publication date: May 23, 2024Inventors: Ryan KEECH, Nicholas MINUTILLO, Anand MURTHY, Aaron BUDREVICH, Peter WELLS
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Patent number: 11973143Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.Type: GrantFiled: March 28, 2019Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Ryan Keech, Benjamin Chu-Kung, Subrina Rafique, Devin Merrill, Ashish Agrawal, Harold Kennel, Yang Cao, Dipanjan Basu, Jessica Torres, Anand Murthy
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Publication number: 20240136277Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: ApplicationFiled: December 22, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Patent number: 11935887Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.Type: GrantFiled: March 28, 2019Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Ryan Keech, Nicholas Minutillo, Anand Murthy, Aaron Budrevich, Peter Wells
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Patent number: 11929320Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: GrantFiled: March 30, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Publication number: 20240014268Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Ryan KEECH, Anand S. MURTHY, Nicholas G. MINUTILLO, Suresh VISHWANATH, Mohammad HASAN, Biswajeet GUHA, Subrina RAFIQUE
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Patent number: 11804523Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: GrantFiled: September 24, 2019Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Ryan Keech, Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad Hasan, Biswajeet Guha, Subrina Rafique
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Publication number: 20230197729Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Inventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Ritesh Jhaveri
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Publication number: 20230095191Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Koustav Ganguly, Ryan Keech, Anand Murthy, Mohammad Hasan, Pratik Patel, Tahir Ghani, Subrina Rafique
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Patent number: 11610889Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).Type: GrantFiled: September 28, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Ritesh Jhaveri
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Patent number: 11552169Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: GrantFiled: March 27, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Suresh Vishwanath
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Patent number: 11482621Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.Type: GrantFiled: September 26, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Willy Rachmady, Patrick Morrow, Aaron Lilak, Rishabh Mehandru, Cheng-Ying Huang, Gilbert Dewey, Kimin Jun, Ryan Keech, Anh Phan, Ehren Mannebach
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Publication number: 20220223519Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Applicant: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Publication number: 20220199402Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Koustav Ganguly, Ryan Keech, Harold Kennel, Willy Rachmady, Ashish Agrawal, Glenn Glass, Anand Murthy, Jack Kavalieros
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Publication number: 20220199468Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey, Jessica Torres, Jack Kavalieros, Matthew Metz, Ryan Keech, Koustav Ganguly, Anand Murthy
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Patent number: 11328988Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: GrantFiled: December 27, 2019Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Publication number: 20220102521Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Gilbert DEWEY, Nazila HARATIPOUR, Siddharth CHOUKSEY, Jack T. KAVALIEROS, Jitendra Kumar JHA, Matthew V. METZ, Mengcheng LU, Anand S. MURTHY, Koustav GANGULY, Ryan KEECH, Glenn A. GLASS, Arnab SEN GUPTA
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Publication number: 20220093586Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
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Patent number: 11244943Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.Type: GrantFiled: December 27, 2019Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
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Publication number: 20210407996Abstract: Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Ashish AGRAWAL, Brennen MUELLER, Jack T. KAVALIEROS, Jessica TORRES, Kimin JUN, Siddharth CHOUKSEY, Willy RACHMADY, Koustav GANGULY, Ryan KEECH, Matthew V. METZ, Anand S. MURTHY