Patents by Inventor Ryan L. Carlson
Ryan L. Carlson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9746903Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.Type: GrantFiled: August 11, 2015Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson, Stephen H. Gunther
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Patent number: 9606602Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2014Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson
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Patent number: 9558127Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.Type: GrantFiled: September 9, 2014Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Stanislav Shwartsman, Robert S. Chappell, Ronak Singhal, Ryan L. Carlson, Raanan Sade, Omar M. Shaikh, Liron Zur, Yiftach Gilad
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Publication number: 20160283232Abstract: A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Raanan Sade, Ryan L. Carlson, Larisa Novakovsky, Erik G. Hallnor, Ravi Rajwar, Roman Dementiev
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Publication number: 20160070651Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.Type: ApplicationFiled: September 9, 2014Publication date: March 10, 2016Inventors: Stanislav Shwartsman, Robert S. Chappell, Ronak Singhal, Ryan L. Carlson, Raanan Sade, Omar M. Shaikh, Liron Zur, Yiftach Gilad
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Publication number: 20150378412Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson
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Publication number: 20150346804Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson, Stephen H. Gunther
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Patent number: 9134788Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.Type: GrantFiled: December 29, 2011Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson, Stephen H. Gunther
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Patent number: 9038949Abstract: An assembly for shielding an aircraft from electromagnetic energy may include a window mounting configured to be conductively coupled to an aperture in a fuselage of an aircraft. The window mounting may include a window pane having an electromagnetically-reflective coating for reflecting electromagnetic energy. The window pane may remain electrically isolated from the fuselage prior to the electromagnetic energy exceeding a frequency of approximately 1 GHz. The window mounting may further include a capacitive gasket capacitively coupling the window pane to the fuselage after the frequency of the electromagnetic energy reflected by the window pane exceeds approximately 1 GHz.Type: GrantFiled: May 5, 2014Date of Patent: May 26, 2015Assignee: The Boeing CompanyInventors: Kenneth P. Kirchoff, Patrick M. Njeim, Thomas K. Morrow, Joel J. Peterson, Michael R. Sirkis, Ryan L. Carlson, Bruce J. Donham, Jim Sears
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Patent number: 8924651Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.Type: GrantFiled: April 16, 2013Date of Patent: December 30, 2014Assignee: Intel CorporationInventors: Perry P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
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Publication number: 20140284425Abstract: An assembly for shielding an aircraft from electromagnetic energy may include a window mounting configured to be conductively coupled to an aperture in a fuselage of an aircraft. The window mounting may include a window pane having an electromagnetically-reflective coating for reflecting electromagnetic energy. The window pane may remain electrically isolated from the fuselage prior to the electromagnetic energy exceeding a frequency of approximately 1 GHz. The window mounting may further include a capacitive gasket capcaitively coupling the window pane to the fuselage after the frequency of the electromagnetic energy reflected by the window pane exceeds approximately 1 GHz.Type: ApplicationFiled: May 5, 2014Publication date: September 25, 2014Applicant: The Boeing CompanyInventors: Kenneth P. Kirchoff, Patrick M. Njeim, Thomas K. Morrow, Joel J. Peterson, Michael R. Sirkis, Ryan L. Carlson, Bruce J. Donham, Jim Sears
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Patent number: 8800926Abstract: A system for shielding an aircraft from electromagnetic energy includes a fuselage, aperture, window mounting, and window plug. The fuselage provides an electrically conductive envelope. The aperture is disposed in the fuselage. The window mounting spans the aperture. The window plug spans the aperture. The window mounting and the window plug are electrically coupled to the fuselage and provide an electrical path spanning the aperture.Type: GrantFiled: June 18, 2007Date of Patent: August 12, 2014Assignee: The Boeing CompanyInventors: Kenneth P. Kirchoff, Patrick M. Njeim, Thomas K. Morrow, Joel J. Peterson, Michael R. Sirkis, Ryan L. Carlson, Bruce J. Donham, Jim Sears
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Publication number: 20140136795Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.Type: ApplicationFiled: April 16, 2013Publication date: May 15, 2014Inventors: PERRY P. TANG, HEMANT G. ROTITHOR, RYAN L. CARLSON, NAGI ABOULENEIN
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Patent number: 8631207Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.Type: GrantFiled: December 26, 2009Date of Patent: January 14, 2014Assignee: Intel CorporationInventors: Zhen Fang, Meenakshisundara R. Chinthamani, Li Zhao, Milind B. Kamble, Ravishankar Iyer, Seung Eun Lee, Robert S. Chappell, Ryan L. Carlson
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Patent number: 8443151Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.Type: GrantFiled: November 9, 2009Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Puqi P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
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Publication number: 20120221871Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.Type: ApplicationFiled: December 29, 2011Publication date: August 30, 2012Applicant: Intel CorporationInventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson, Stephen H. Gunther
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Publication number: 20110161595Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.Type: ApplicationFiled: December 26, 2009Publication date: June 30, 2011Inventors: Zhen Fang, Meenakshisundara R. Chinthamani, Li Zhao, Milind B. Kamble, Ravishankar Iyer, Seung Eun Lee, Robert S. Chappell, Ryan L. Carlson
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Publication number: 20110113199Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Inventors: Puqi P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
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Patent number: 7913385Abstract: To attenuate electromagnetic energy, a capacitive bond between a window and a frame is provided by a capacitive coupling. This capacitive coupling includes an elastomeric matrix and a conductive media. The elastomeric matrix provides a seal between the window and the frame. The conductive media is bound to the matrix and conducts electromagnetic energy from the window to the frame.Type: GrantFiled: December 2, 2005Date of Patent: March 29, 2011Assignee: The Boeing CompanyInventors: Ryan L. Carlson, Bruce J. Donham, Jim Sears
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Publication number: 20070137117Abstract: To attenuate electromagnetic energy, a capacitive bond between a window and a frame is provided by a capacitive coupling. This capacitive coupling includes an elastomeric matrix and a conductive media. The elastomeric matrix provides a seal between the window and the frame. The conductive media is bound to the matrix and conducts electromagnetic energy from the window to the frame.Type: ApplicationFiled: December 2, 2005Publication date: June 21, 2007Inventors: Ryan L. Carlson, Bruce J. Donham, Jim Sears