Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

Abstract: A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

Abstract: A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.