Abstract: A pulse-width modulation circuit includes an oscillator stage. The oscillator stage includes a first voltage comparator having a first input terminal, a second input terminal and an output terminal. A first capacitor is coupled to the first input terminal of the first voltage comparator. A charging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the charging path having a first resistance. A discharging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the discharging path having a second resistance that is different from the first resistance. A duty cycle of a clock signal generated by the oscillator stage is determined based on a first RC time constant for charging the first capacitor and a second RC time constant for discharging the first capacitor.

Abstract: A radiation tolerant gate driver for power converters with active-clamp reset and active-driven synchronous rectification uses integrated logic drivers for high efficiency and wide input range. A keep alive circuit prevents power train transistors from remaining on for extended durations after a transient or an undervoltage lockout (UVLO) event. Each of the integrated logic drivers includes two gate driver circuits, where one of the gate driver circuits uses the output of the other of the gate driver circuits as input per a logic table of the integrated logic driver, to ensure no shoot-through when the respective power train transistors are turned on and off.

Abstract: A circuit includes a voltage detection path having a first transistor and a second transistor coupled to the first voltage detection path by a first terminal of the second transistor. The first voltage detection path includes: a first current source and a first voltage divider unit coupled to the first current source. The first transistor is coupled to the first voltage divider unit by a first terminal of the first transistor. A first voltage value at a second terminal of the first transistor is configured to switch between a first high voltage value and a first low voltage value at least partially based on a first detection voltage value provided at the first terminal of the first transistor by the first voltage divider unit. A second voltage at a second terminal of the second transistor is configured to switch between a second high voltage value and a second low voltage value at least partially based on the first voltage value at the second terminal of the first transistor.