Patents by Inventor RYAN SCOTT SMITH

RYAN SCOTT SMITH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11819847
    Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about ?1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ryan Scott Smith, Roger Quon, David Collins, George Odlum, Raghav Sreenivasan, Joseph R. Johnson
  • Publication number: 20220270979
    Abstract: Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Ryan Scott Smith, Kai Wu, Nicolas Louis Gabriel Breil
  • Publication number: 20220242725
    Abstract: Embodiments of the present disclosure provide methods of forming solid state dual pore sensors which may be used for biopolymer sequencing and dual pore sensors formed therefrom. In one embodiment, a method of forming a dual pore sensor includes providing a pattern in a surface of a substrate. Generally, the pattern features two fluid reservoirs separated by a divider wall. The method further includes depositing a layer of sacrificial material into the two fluid reservoirs, depositing a membrane layer, patterning two nanopores through the membrane layer, removing the sacrificial material from the two fluid reservoirs, and patterning one or more fluid ports and a common chamber.
    Type: Application
    Filed: April 15, 2020
    Publication date: August 4, 2022
    Inventors: Joseph R. JOHNSON, Roger QUON, Archana KUMAR, Ryan Scott SMITH, Jeremiah HEBDING, Raghav SREENIVASAN
  • Publication number: 20220236250
    Abstract: Embodiments of the present disclosure provide methods of forming solid state dual pore sensors which may be used for biopolymer sequencing and dual pore sensors formed therefrom. In one embodiment, a dual pore sensor features a substrate having a patterned surface comprising two recessed regions spaced apart by a divider wall and a membrane layer disposed on the patterned surface. The membrane layer, the divider wall, and one or more surfaces of each of the two recessed regions collectively define a first fluid reservoir and a second fluid reservoir. A first nanopore is disposed through a portion of the membrane layer disposed over the first fluid reservoir and a second nanopore is disposed through a portion of the membrane layer disposed over the second fluid reservoir. Herein, opposing surfaces of the divider wall are sloped to each form an angle of less than 90° with a respective reservoir facing surface of the membrane layer.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 28, 2022
    Inventors: Joseph R. JOHNSON, Roger QUON, Archana KUMAR, Ryan Scott SMITH, Jeremiah HEBDING, Raghav SREENIVASAN
  • Publication number: 20220016628
    Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about ?1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 20, 2022
    Inventors: Ryan Scott SMITH, Roger QUON, David COLLINS, George ODLUM, Raghav SREENIVASAN, Joseph R. JOHNSON
  • Patent number: 10078107
    Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jaime Bravo, Vikrant Chauhan, Ryan Scott Smith
  • Publication number: 20170115337
    Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jaime BRAVO, Vikrant CHAUHAN, Ryan Scott SMITH
  • Publication number: 20170052014
    Abstract: At least one method, apparatus, and system for determining a distance between layers of a semiconductor device and, if desired, modifying a semiconductor device manufacturing process in view of the determined distance. The system comprises and the methods make use of a test circuit comprising a resistor, at least one of an inductor and a capacitor, a first terminal and a second terminal each configured to electrically connect to a first layer circuit and a second layer circuit of a semiconductor device.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 23, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: RYAN SCOTT SMITH