Patents by Inventor Ryan Sporer
Ryan Sporer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230393340Abstract: IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: RYAN SPORER, KAREN NUMMY, KEITH DONEGAN, THOMAS HOUGHTON, YUSHENG BIAN, TAKAKO HIROKAWA, KENNETH GIEWONT
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Patent number: 11650382Abstract: Structures including an optical component, such as an edge coupler, and methods of fabricating a structure that includes an optical component, such as an edge coupler. The structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is positioned vertically over the substrate and the dielectric layer, and the optical component overlaps with the sealed cavity in the substrate.Type: GrantFiled: October 26, 2021Date of Patent: May 16, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Ryan Sporer, Yusheng Bian, Takako Hirokawa
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Publication number: 20230128786Abstract: Structures including an optical component, such as an edge coupler, and methods of fabricating a structure that includes an optical component, such as an edge coupler. The structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is positioned vertically over the substrate and the dielectric layer, and the optical component overlaps with the sealed cavity in the substrate.Type: ApplicationFiled: October 26, 2021Publication date: April 27, 2023Inventors: Ryan Sporer, Yusheng Bian, Takako Hirokawa
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Publication number: 20230047046Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Inventors: Ryan Sporer, George R. Mulfinger, Yusheng Bian
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Publication number: 20230038887Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.Type: ApplicationFiled: August 5, 2021Publication date: February 9, 2023Inventors: Ryan Sporer, George R. Mulfinger, Yusheng Bian
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Patent number: 11569268Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.Type: GrantFiled: August 5, 2021Date of Patent: January 31, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Ryan Sporer, George R. Mulfinger, Yusheng Bian
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Patent number: 11217678Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.Type: GrantFiled: November 11, 2019Date of Patent: January 4, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel
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Patent number: 11127843Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.Type: GrantFiled: January 3, 2020Date of Patent: September 21, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Judson Holt, Alexander Derrickson, Ryan Sporer, George R. Mulfinger, Alexander Martin, Jagar Singh
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Patent number: 11094805Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.Type: GrantFiled: January 17, 2020Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Alexander Derrickson, Edmund K. Banghart, Alexander Martin, Ryan Sporer, Jagar Singh, Katherina Babich, George R. Mulfinger
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Publication number: 20210226044Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Alexander Derrickson, Edmund K. Banghart, Alexander Martin, Ryan Sporer, Jagar Singh, Katherina Babich, George R. Mulfinger
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Publication number: 20210091212Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.Type: ApplicationFiled: January 3, 2020Publication date: March 25, 2021Inventors: Judson Holt, Alexander Derrickson, Ryan Sporer, George R. Mulfinger, Alexander Martin, Jagar Singh
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Publication number: 20200083346Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.Type: ApplicationFiled: November 11, 2019Publication date: March 12, 2020Inventors: George Robert MULFINGER, Ryan SPORER, Rick J. CARTER, Peter BAARS, Hans-Jürgen THEES, Jan HÖNTSCHEL
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Patent number: 10522655Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.Type: GrantFiled: September 21, 2017Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel
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Patent number: 10326007Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.Type: GrantFiled: July 3, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt
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Patent number: 10217660Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.Type: GrantFiled: July 18, 2017Date of Patent: February 26, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ryan Sporer, George Mulfinger
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Publication number: 20190043967Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.Type: ApplicationFiled: July 3, 2018Publication date: February 7, 2019Inventors: George Robert MULFINGER, Ryan SPORER, Timothy J. MCARDLE, Judson Robert HOLT
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Publication number: 20190027400Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Ryan Sporer, George Mulfinger
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Publication number: 20180315832Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.Type: ApplicationFiled: July 5, 2018Publication date: November 1, 2018Inventors: George Robert MULFINGER, Dina H. TRIYOSO, Ryan SPORER
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Patent number: 10056381Abstract: Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first plurality of fins are formed and are each located in a respective trench extending from the substrate through the first layer. A second plurality of fins are formed and are each located in a respective trench extending from the substrate through the second layer. The first dopant is transferred from the first layer to a first section in each of the first plurality of fins and the second dopant is transferred from the second layer to a first section in each of the second plurality of fins.Type: GrantFiled: September 8, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ryan Sporer, Amy Child, George Mulfinger
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Patent number: 10050119Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.Type: GrantFiled: September 2, 2016Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: George Robert Mulfinger, Dina H. Triyoso, Ryan Sporer