Patents by Inventor Ryan Tasuo Hirose
Ryan Tasuo Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10032517Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: April 15, 2015Date of Patent: July 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Publication number: 20180166140Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: June 14, 2018Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 9899089Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: September 24, 2013Date of Patent: February 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Publication number: 20160005475Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: January 7, 2016Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 8908438Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.Type: GrantFiled: October 29, 2013Date of Patent: December 9, 2014Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Bogdan I. Georgescu, Ashish Ashok Amonkar, Vijay Raghavan, Cristinel Zonte, Sean B. Mulholland
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Patent number: 7586333Abstract: Disclosed are a circuit and a method for a high speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation. The circuit includes a low voltage driver. A gate bootstrapped transistor is coupled to the low voltage driver. A first transistor is coupled to an output terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal. A second transistor is coupled to a gate terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal.Type: GrantFiled: December 20, 2007Date of Patent: September 8, 2009Assignee: Cypress Semiconductor CorporationInventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
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Patent number: 7545694Abstract: Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.Type: GrantFiled: August 16, 2007Date of Patent: June 9, 2009Assignee: Cypress Semiconductor CorporationInventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
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Patent number: 7471135Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.Type: GrantFiled: December 5, 2006Date of Patent: December 30, 2008Assignee: Cypress Semiconductor Corp.Inventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
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Publication number: 20080130375Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: CYPRESS SEMICONDUCTOR CORP.Inventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
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Publication number: 20080042691Abstract: Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.Type: ApplicationFiled: August 16, 2007Publication date: February 21, 2008Inventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose