Abstract: A solar power generation system includes a string, an inverter a first shut-off device, and a second shut-off device. The string includes a plurality of solar cell module groups connected in series with each other. Each of the solar cell module groups includes one or a plurality of solar cell modules connected in series. The first shut-off device cuts off a connection between the plurality of solar cell module groups connected to a first electric path in response to a first control signal from the inverter. The second shut-off device is connected to the first shut-off device in a two-way communicable manner, is driven by an electrical power supplied from the first shut-off device, and cuts off a connection between the plurality of solar cell module groups connected to a second electric path in response to a second control signal from the first shut-off device.

Abstract: A solar power generation system includes a string, an inverter a first shut-off device, and a second shut-off device. The string includes a plurality of solar cell module groups connected in series with each other. The first shut-off device cuts off a connection between the plurality of solar cell module groups connected to a first electric path connecting between the plurality of solar cell module groups in response to a first control signal from the inverter. The second shut-off device is connected to the first shut-off device in a two-way communicable manner by a communication system different from power line communication and cuts off a connection between the solar cell module groups connected to a second electric path connecting between the plurality of solar cell module groups in response to a second control signal output from the first shut-off device by a communication system different from power line communication.

Abstract: A solar power generation system includes a string, an inverter a first shut-off device, and a second shut-off device. The string includes a plurality of solar cell module groups connected in series. The first shut-off device is connected to a first electric path connecting between the plurality of solar cell module groups. The second shut-off device is connected to a second electric path connecting between the plurality of solar cell module groups. The first shut-off device cuts off a connection between the plurality of solar cell module groups connected to the first electric path in response to a first control signal from the inverter. The second shut-off device is driven by an electrical power supplied from the first shut-off device and cuts off a connection between the solar cell module groups connected to the second electric path in response to a second control signal from the first shut-off device.

Abstract: Disclosed is a charge transfer complex capable of obtaining a curable resin composition having an excellent balance between curability and storage stability when used as an epoxy-resin curing agent. The charge transfer complex has an imidazole moiety as an electron donor moiety. The charge transfer complex may be an assembly wherein electrons included in a compound (a) having an imidazole moiety are accepted by a compound (b) having an electron acceptor moiety, or may be a compound having an imidazole moiety and an electron acceptor moiety in its molecule, and the electron acceptor moiety accepts electrons included in the imidazole moiety.

Abstract: A touch detecting apparatus includes an electrostatic sensor provided on an object; and a processor configured to detect whether a hand touches the object based on a capacitance measured by the electrostatic sensor. The processor is configured to, in response to the capacitance being greater than or equal to a first touch threshold, detect that the hand touches the object, and, for a second predetermined time from when a change amount of the capacitance during a first predetermined time becomes greater than or equal to a noise threshold, continue a state where a correction value has been added to the first touch threshold.

Abstract: An electric drive apparatus includes a rotating electric machine and a transmission. The rotating electric machine includes a rotor, a stator and a first housing. The transmission includes a motive power transmitting unit, a second housing provided integrally with the first housing, and lubricating oil provided in the second housing to lubricate the motive power transmitting unit. The stator includes a stator coil that has first and second coil end parts respectively protruding from first and second axial end faces of a stator core. Each of phase windings of the stator coil has turn portions included in the first coil end part and joints included in the second coil end part. The second coil end part is located on the same axial side of the stator core as the transmission whereas the first coil end part is located on the opposite axial side of the stator core to the transmission.

Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: A navigation device includes a processor. The processor collects captured images that have been captured by an imaging device mounted at a vehicle, sets a destination, and determines a route to the destination based on the captured images that have been collected.

Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: There is provided a device control apparatus which makes it possible to dispense with device monitoring (polling) by a client apparatus to thereby reduce traffic on a network. A device server 200 acquires, according to device information for identifying a device locally connected to the device server 200, at least one of a trigger detection algorithm and a definition file for monitoring a state change of the device identified based on the device information, and monitors the locally connected device based on at least one of the acquired trigger detection algorithm and definition file. Then, when a state change of the device is detected, the device server 200 sends a trigger notification indicative of the detection of the state change to a client PC 100 via a network 500, and starts a session with the client PC 100 in response to a connection request from the client PC 100 having received the trigger notification.

Abstract: A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.

Abstract: A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.