Patents by Inventor Ryo Haruta
Ryo Haruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080122050Abstract: A power semiconductor device in which a semiconductor element is die-mount-connected onto a lead frame in a Pb-free manner. In a die-mount-connection with a large difference of thermal expansion coefficient between a semiconductor element 1 and a lead frame 2, the connection is made with an intermetallic compound 200 having a melting point of 260° C. or higher or a Pb-free solder having a melting point of 260° C. or higher to 400° C. or lower, at the same time, the thermal stress produced in temperature cycles is buffered by a metal layer 100 having a melting point of 260° C. or higher. A Pb-free die-mount-connection which does not melt at the time of reflowing but have no chip crack to occur according to thermal stress can be achieved.Type: ApplicationFiled: June 15, 2005Publication date: May 29, 2008Inventors: Osamu Ikeda, Masahide Okamoto, Ryo Haruta, Hidemasa Kagii, Hiroi Oka, Hiroyuki Nakamura
-
Patent number: 6897570Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.Type: GrantFiled: January 9, 2003Date of Patent: May 24, 2005Assignee: Renesas Technology, CorporationInventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
-
Patent number: 6887739Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 3, 2003Date of Patent: May 3, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6844219Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.Type: GrantFiled: May 2, 2002Date of Patent: January 18, 2005Assignee: Renesas Technology Corp.Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
-
Patent number: 6764878Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 12, 2002Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6759279Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: August 8, 2002Date of Patent: July 6, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20040005733Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: ApplicationFiled: July 3, 2003Publication date: January 8, 2004Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20030230809Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.Type: ApplicationFiled: January 9, 2003Publication date: December 18, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
-
Patent number: 6621160Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: GrantFiled: January 16, 2002Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
-
Patent number: 6590275Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: January 31, 2002Date of Patent: July 8, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6563212Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: GrantFiled: January 16, 2002Date of Patent: May 13, 2003Assignee: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
-
Patent number: 6512176Abstract: In a ball grid array type semiconductor device mounted on a printed wiring board, the external terminals can be prevented from being broken down even when the ambient temperature on the device is repeatedly changed. A flexible adhesive member for gluing the semiconductor chip to an insulating tape is provided to cover up to a region including the lands to which the external terminals are bonded and which are provided on the insulating tape surface. The flexible adhesive member for covering the lands may be replaced by a flexible low-elasticity member.Type: GrantFiled: January 16, 2002Date of Patent: January 28, 2003Assignee: Hitachi, Ltd.Inventors: Akihiro Yaguchi, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20020192872Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: ApplicationFiled: August 8, 2002Publication date: December 19, 2002Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20020182776Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: ApplicationFiled: July 12, 2002Publication date: December 5, 2002Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6476466Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: January 31, 2002Date of Patent: November 5, 2002Assignee: Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6476467Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: June 1, 2001Date of Patent: November 5, 2002Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
-
Patent number: 6465876Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.Type: GrantFiled: November 19, 1997Date of Patent: October 15, 2002Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
-
Patent number: 6448111Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: June 15, 2000Date of Patent: September 10, 2002Assignees: Hitachi Hokkai Semiconductor, Ltd., Hitachi, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6437428Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: June 16, 2000Date of Patent: August 20, 2002Assignee: Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20020105070Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: ApplicationFiled: January 16, 2002Publication date: August 8, 2002Applicant: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo