Patents by Inventor Ryo Maniwa

Ryo Maniwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6111479
    Abstract: A laminate printed circuit board loaded with transistors, ICs (Integrated Circuits) or LSIs (Large Scale Integrated Circuits) and a method of producing the same are disclosed. The circuit board includes a signal layer, a ground layer and a power supply layer sequentially laminated with the intermediary of insulation layers. An impedance adding circuit is formed in the power supply layer. A magnetic layer is positioned at least above or at least blow the impedance adding circuit. The circuit board with this configuration reduces power supply noise to a noticeable degree.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: August 29, 2000
    Assignee: NEC Corporation
    Inventors: Osamu Myohga, Shiro Yoshida, Mitsuo Saito, Yuzo Shimada, Hirokazu Tohya, Ryo Maniwa
  • Patent number: 5526564
    Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 18, 1996
    Assignee: NEC Corporation
    Inventors: Tutomu Ohshima, Hidebumi Ohnuki, Ryo Maniwa
  • Patent number: 5480675
    Abstract: An apparatus for plating a printed circuit board including a non-through hole for connecting between a surface conductive layer and an interlayer wiring layer has a jig, a vessel, a supporting body carrying the jig for causing it to vibrate and swing in a plating liquid contained in the vessel, and a vacuum pump connected to the vessel for exhausting the air in the vessel thereby enhancing removal of bubbles in the non-through hole. A method of plating a printed circuit board includes the step of reducing the pressure inside the vessel simultaneously with the printed circuit board being subjected to the vibration and swinging actions thereby to remove a bubble existing inside the non-through hole. The removal of the bubble makes it possible to have a uniform plating film formed in an inner wall of the non-through hole and ensures the reliable electric connection to be established through the non-through hole between a surface conductive layer and interlayer conductive layers.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: January 2, 1996
    Assignee: NEC Corporation
    Inventors: Tomoo Murakami, Hidebumi Ohnuki, Takanori Tsunoda, Ryo Maniwa
  • Patent number: 5455393
    Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: October 3, 1995
    Assignee: NEC Corporation
    Inventors: Tutomu Ohshima, Hidebumi Ohnuki, Ryo Maniwa
  • Patent number: 5258094
    Abstract: A multilayered board is formed by applying a photosensitive insulating resin layer on a laminated plate on which via holes and a circuit pattern are formed, followed by the formation of photoviaholes through the photoprinting method, plating and etching. Then, the multilayered board is adhered to another multilayered board prepared in the same manner through a prepreg layer and a conductive paste while applying heat and pressure to give a multilayer printed wiring board. According to this method, electrical connections between the conductive layer of the upper-most layer and the inner conductive layers, between the inner conductive layers, and between the lower-most conductive layer and the inner conductive layers can be achieved through the photoviaholes and the conductive paste. Therefore, it is not necessary to form through-holes for the electrical connection therebetween. The multilayer printed wiring boards can be substantially improved in the number of layers and wiring density thereof.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: November 2, 1993
    Assignee: NEC Corporation
    Inventors: Seiji Furui, Ryo Maniwa, Kiminori Ishido, Keisuke Okada
  • Patent number: 5218761
    Abstract: A laminated board in which each of prepreg sheets is sandwiched between an internal printed wiring board which is provided with wirings and each of external printed wiring board which is provided with wirings on the outermost surface thereof is formed with through-holes by drilling. A thin copper plating layer is formed on the surfaces of the laminated board including the inner wall of the through-hole. Then, an alkali-soluble photoresist film is selectively formed on the surface of the thin copper plating layer and a thick copper plating layer is formed. The thin copper plating layer is removed by using the thick copper plating layer as a mask to forme through holes and wirings. The through holes and wirings can be thus formed without using the additive process. Environmental pollution due to use of organic solvents can be prevented by avoiding the use of an organic solvent-soluble resist film having a strong resistance to alkalis.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: June 15, 1993
    Assignee: NEC Corporation
    Inventors: Ryo Maniwa, Hidebumi Ohnuki