Patents by Inventor Ryo Nakagaki
Ryo Nakagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783625Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: GrantFiled: September 29, 2017Date of Patent: September 22, 2020Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
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Patent number: 10203851Abstract: Provided is a GUI including: an unadded pane region that hierarchically displays folders which are sets of images having no class information added thereto; an image pane region that displays the images displayed in the unadded pane region, the displayed images having no classification added thereto; and a class pane region that displays images having classification added thereto, wherein by externally inputting class information for one image having the class information added thereto, the input class information is displayed.Type: GrantFiled: November 26, 2012Date of Patent: February 12, 2019Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
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Publication number: 20180025482Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: ApplicationFiled: September 29, 2017Publication date: January 25, 2018Inventors: Minoru HARADA, Ryo NAKAGAKI, Fumihiko FUKUNAGA, Yuji TAKAGI
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Patent number: 9811897Abstract: The purpose of the present invention is to easily extract, from samples to be observed, defect candidates that can be labeled as a defect or “nuisance” (a part for which a manufacturing tolerance or the like is erroneously detected) and to allow parameters pertaining to observation processing to be easily adjusted. This defect observation method comprises: an imaging step to image, on the basis of defect information from an inspection device, an object to be inspected and obtain a defect image and a reference image corresponding to the defect image; a parameter determining step to determine a first parameter to be used in the defect extraction by using a first feature set distribution acquired from the reference image and the defect image captured in the imaging step and a second feature net distribution acquired from the reference image; and an observing step to observe using the first parameter determined in the parameter determining step.Type: GrantFiled: December 6, 2013Date of Patent: November 7, 2017Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Minoru Harada, Yuji Takagi, Ryo Nakagaki, Takehiro Hirai, Hirohiko Kitsuki
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Patent number: 9799112Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: GrantFiled: February 6, 2013Date of Patent: October 24, 2017Assignee: Hitachi High-Technologies CorporationInventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
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Patent number: 9685301Abstract: The present invention provides a charged-particle radiation apparatus with a defect observation device for observing defects on a sample, the apparatus including a control unit and a display unit. The control unit is configured to execute a drift correction process on one or more images acquired with the defect observation device under a plurality of correction conditions, and display the plurality of correction conditions and a plurality of corrected images obtained through execution of the drift correction process in association with each other, as a first screen on the display unit.Type: GrantFiled: October 11, 2013Date of Patent: June 20, 2017Assignee: Hitachi High-Technologies CorporationInventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
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Patent number: 9582875Abstract: Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.Type: GrantFiled: April 1, 2013Date of Patent: February 28, 2017Assignee: Hitachi High-Technologies CorporationInventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
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Patent number: 9569836Abstract: Cases in which defects are analyzed in a manufacturing process stage in which a pattern is not formed or in a manufacturing process in which a pattern formed on a lower layer does not appear in the captured image are increasing. However, in these cases, there is a problem of not being able to synthesize a favorable reference image and failing to detect a defect when a periodic pattern cannot be recognized in the pattern. In the present invention, a defect occupation rate, which is the percentage of an image being inspected occupied by a defect region, is found, it is determined whether the defect occupation rate is higher or lower than a threshold, and, in accordance with the determination results, it is determined whether to create, as the reference image, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected.Type: GrantFiled: November 29, 2013Date of Patent: February 14, 2017Assignee: Hitachi High-Technologies CorporationInventors: Takehiro Hirai, Ryo Nakagaki, Minoru Harada
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Patent number: 9401015Abstract: In automatic defect classification, a classification recipe must be set for each defect observation device. If a plurality of devices operate at the same stage, the classification class in the classification recipes must be the same. Problems have arisen whereby differences occur in the classification class in different devices when a new classification recipe is created. This defect classification system has a classification recipe storage unit; an information specification unit, the stage of a stored image, and device information. A corresponding defect specification unit specifies images of the same type of defect from images obtained from different image pickup devices at the same stage. An image conversion unit converts the images obtained from the different image pickup devices at the same stage into comparable similar images; and a recipe update unit records the classification classes in the classification recipes corresponding to the specified images of the same type of defect.Type: GrantFiled: April 16, 2012Date of Patent: July 26, 2016Assignee: Hitachi High-Technologies CorporationInventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
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Patent number: 9390490Abstract: In performing a programmed-point inspection of a circuit pattern using a review SEM, stable inspection can be performed while suppressing the generation of a false report even when a variation in a circuit pattern to be inspected is large. SEM images that are obtained by sequentially imaging a predetermined circuit pattern using the review SEM are stored into a storage unit. Images that meet a set condition are selected from the stored SEM images, and averaged to create an average image (GP image). By performing pattern check by GP comparison using this GP image, an inspection can be performed while suppressing the generation of a false report even when a variation in the circuit patterns is large.Type: GrantFiled: December 22, 2010Date of Patent: July 12, 2016Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yuji Takagi, Minoru Harada, Ryo Nakagaki, Naoki Hosoya, Toshifumi Honda, Takehiro Hirai
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Patent number: 9342879Abstract: A method for reviewing defect, comprising the steps of: as an image acquisition step, imaging a surface of a sample using arbitrary image acquisition condition selected from a plurality of image acquisition conditions and obtaining a defect image; as a defect position calculation step, proceeding the defect image obtained by the image acquisition step and calculating a defect position on the surface of the sample; as a defect detection accuracy calculation step, obtaining a defect detection accuracy of the defect position calculated by the defect position calculation step; and as a conclusion determination step, determinating whether the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined requirement or not; wherein until it is determined that the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined in the conclusion determination step, the image acquisition condition is selected from the plurality ofType: GrantFiled: July 6, 2012Date of Patent: May 17, 2016Assignee: Hitachi Hich-Technologies CorporationInventors: Yohei Minekawa, Kenji Nakahira, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
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Patent number: 9335277Abstract: A region-of-interest determination apparatus includes: a calculation unit and a region determination unit. The calculation unit calculates a degree of a defect based on at least a plurality of kinds of defect attribute information regarding defect data. The defect data includes an image corresponding to a defect position detected on a specimen by inspection thereof or an image corresponding to a defect position predicted to be likely to develop a defect on the specimen, where both images are obtained by imaging. The region determination unit extracts the defect data of which the degree is higher than a predetermined level, and determines the region to be observed or inspected on the specimen based on the extracted defect data.Type: GrantFiled: July 9, 2012Date of Patent: May 10, 2016Assignee: Hitachi High-Technologies CorporationInventors: Ryo Nakagaki, Takehiro Hirai, Kenji Obara
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Patent number: 9311697Abstract: Disclosed is a method of inspecting an object to be inspected in a semiconductor manufacturing process, for resolving the problem to increase defect detection sensitivity. An image capture means is used to image capture a designated area of the object to be inspected; a defect is detected in the captured image; a circuit pattern is recognized from the captured image; a characteristic value is computed, relating to an image tone and shape, from the detected defect; a characteristic value is computed, relating to the image tone and shape, from the recognized circuit pattern; either a specified defect or circuit pattern is filtered and extracted from the detected defect and the recognized circuit pattern; a mapping characteristic value is determined from the characteristic value of either the filtered and extracted specified defect or circuit pattern; and the distribution of the determined characteristic values is displayed onscreen in a map format.Type: GrantFiled: April 1, 2011Date of Patent: April 12, 2016Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Minoru Harada, Ryo Nakagaki, Takehiro Hirai, Naoki Hosoya
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Publication number: 20150332445Abstract: The purpose of the present invention is to easily extract, from samples to be observed, defect candidates that can be labeled as a defect or “nuisance” (a part for which a manufacturing tolerance or the like is erroneously detected) and to allow parameters pertaining to observation processing to be easily adjusted. This defect observation method comprises: an imaging step to image, on the basis of defect information from an inspection device, an object to be inspected and obtain a defect image and a reference image corresponding to the defect image; a parameter determining step to determine a first parameter to be used in the defect extraction by using a first feature set distribution acquired from the reference image and the defect image captured in the imaging step and a second feature net distribution acquired from the reference image; and an observing step to observe using the first parameter determined in the parameter determining step.Type: ApplicationFiled: December 6, 2013Publication date: November 19, 2015Inventors: Minoru HARADA, Yuji TAKAGI, Ryo NAKAGAKI, Takehiro HIRAI, Hirohiko KITSUKI
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Publication number: 20150302568Abstract: Cases in which defects are analyzed in a manufacturing process stage in which a pattern is not formed or in a manufacturing process in which a pattern formed on a lower layer does not appear in the captured image are increasing. However, in these cases, there is a problem of not being able to synthesize a favorable reference image and failing to detect a defect when a periodic pattern cannot be recognized in the pattern. In the present invention, a defect occupation rate, which is the percentage of an image being inspected occupied by a defect region, is found, it is determined whether the defect occupation rate is higher or lower than a threshold, and, in accordance with the determination results, it is determined whether to create, as the reference image, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected.Type: ApplicationFiled: November 29, 2013Publication date: October 22, 2015Inventors: Takehiro HIRAI, Ryo NAKAGAKI, Minoru HARADA
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Publication number: 20150279614Abstract: The present invention provides a charged-particle radiation apparatus with a defect observation device for observing defects on a sample, the apparatus including a control unit and a display unit. The control unit is configured to execute a drift correction process on one or more images acquired with the defect observation device under a plurality of correction conditions, and display the plurality of correction conditions and a plurality of corrected images obtained through execution of the drift correction process in association with each other, as a first screen on the display unit.Type: ApplicationFiled: October 11, 2013Publication date: October 1, 2015Inventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
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Patent number: 9082585Abstract: An imaging region of a high-magnification reference image capable of being acquired in a low-magnification field without moving a stage from a position at which a defective region has been imaged at a low magnification is searched for and if the search is successful, an image of the imaging region itself is acquired and the high-magnification reference image is acquired. If the search is unsuccessful, the imaging scheme is switched to that in which the high-magnification reference image is acquired from a chip adjacent to the defective region.Type: GrantFiled: November 27, 2009Date of Patent: July 14, 2015Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Go Kotaki, Atsushi Miyamoto, Ryo Nakagaki, Takehiro Hirai
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Patent number: 9040937Abstract: In a pattern inspection of a semiconductor circuit, to specify a cause of a process defect, not only a distribution on and across wafer of the number of defects but also more detailed, that is, the fact that how many defects occurred where on the semiconductor pattern is needed to be specified in some cases. Accordingly, the present invention aims to provide an apparatus capable of easily specifying a cause of a process defect based upon a positional relationship of a distribution of defect occurrence frequency and a pattern.Type: GrantFiled: March 11, 2013Date of Patent: May 26, 2015Assignee: Hitachi High-Technologies CorporationInventors: Kohei Yamaguchi, Takehiro Hirai, Ryo Nakagaki
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Publication number: 20150139531Abstract: Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.Type: ApplicationFiled: April 1, 2013Publication date: May 21, 2015Inventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
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Publication number: 20150060667Abstract: In a pattern inspection of a semiconductor circuit, to specify a cause of a process defect, not only a distribution on and across wafer of the number of defects but also more detailed, that is, the fact that how many defects occurred where on the semiconductor pattern is needed to be specified in some cases. Accordingly, the present invention aims to provide an apparatus capable of easily specifying a cause of a process defect based upon a positional relationship of a distribution of defect occurrence frequency and a pattern.Type: ApplicationFiled: March 11, 2013Publication date: March 5, 2015Inventors: Kohei Yamaguchi, Takehiro Hirai, Ryo Nakagaki