Abstract: The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

Abstract: In a computer on the transmission side, an NW driver, which is recognized, by the OS, as an NIC driver, stores data to be transmitted and a destination SPA into a memory, and outputs a transaction layer packet (TLP), which has been generated by a first computer, to a PCIe switch. A first NIC logic of the PCIe switch of the PCIe switch corresponding to the first computer on the transmission side adds a system port address (SPA) to the TLP transferred from the first computer, and transfers the data of the TLP to a port associated with a second NIC logic and having an address indicated by the SPA (destination SPA). The second NIC logic having received the data writes the receive data into a memory of a second computer, on the reception side, which is connected to another PCIe switch where the second NIC logic exists.

Abstract: In a computer on the transmission side, an NW driver, which is recognized, by the OS, as an NIC driver, stores data to be transmitted and a destination SPA into a memory, and outputs a transaction layer packet (TLP), which has been generated by a first computer, to a PCIe switch. A first NIC logic of the PCIe switch of the PCIe switch corresponding to the first computer on the transmission side adds a system port address (SPA) to the TLP transferred from the first computer, and transfers the data of the TLP to a port associated with a second NIC logic and having an address indicated by the SPA (destination SPA). The second NIC logic having received the data writes the receive data into a memory of a second computer, on the reception side, which is connected to another PCIe switch where the second NIC logic exists.

Abstract: The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

Abstract: In order to suppress occurrence of a random pattern signal is suppressed without the use of a sideband signal in a long distance data transmission exceeding that defined in a PCIe interface specification, provided is a computer system, including a first component having a transmitting unit which transmits a control signal, a second component having a receiving unit which receives the control signal, a transmission path which connects the first component and the second component along which a signal is transmitted and received, wherein: in case of the transmitting unit of the first component transmits a ternary signal with three states of 0/1/Idle to the receiving unit of the second component, the transmitting unit of the first component substitutes a combination of signals representing 0/1 for a signal representing the Idle state, and transmits the substituted signals instead of the ternary signal to the receiving unit of the second component.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: A mild steel or Fe—Ni alloy used for a shadow mask has TS/0.2% YS ≦1.03.

Abstract: An information processing equipment designed to support the compatibility of a plurality of clocks such as its internal clock and a clock for external bus interface by using only a single wired-in line for supplying the internal clock; and to perform frequency conversion control only in a logical circuit with the internal-to-external clock frequency ratio being N:1 or N:2 for the clocks, wherein the equipment comprises: a signal generator for supplying a common reference clock to itself and peripheral equipment and generating a reference sync signal from the reference clock to synchronize itself and the peripheral equipment; a signal generator for generating its internal clock from the reference clock; a signal generator for generating timing signals to control the timing of access to the external bus in accordance with an internal-to-peripheral clock frequency ratio; and a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with generated timing signals.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

Abstract: An LSI having a logic circuit and a test circuit is provided with a first register which is connected between an LSI input/output pin and the logic circuit and has a first input terminal to be outputted from the first register in accordance with a system clock signal and a second input terminal, a second register which has a first input terminal inputted with an output of the first register and a second input terminal inputted with scan-in data and an output of which is connected to the second input terminal of the first register, a selector circuit which is connected to one of the first input terminal of the second register and the second terminal of the first register and selects one of a signal relating to scan-out data and an output signal of the other register so that the selected signal is inputted to the one input terminal, and a third register which receives an output of the second register and provides the received output as scan-out data in accordance with another clock signal.

Abstract: A reference sync signal for synchronizing with peripheral equipment and an internal clock for an internal operation of a processor system are generated from a reference clock inside the processor system. A base clock is used to generate an internal clock in which a duty of each clock cycle changes. A circuit includes a synchronous counter using a reference sync signal as a reset signal and deciding a count number in accordance with a frequency ratio set in advance, and generates an access timing signal to the peripheral equipment. A conversion circuit synchronously gains access to an external bus operating at a different frequency by using the access timing signal as an enable signal of a latch of an external interface.

Abstract: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

Abstract: An information processing equipment designed to support the compatibility of a plurality of clocks such as its internal clock and a clock for external bus interface by using only a single wired-in line for supplying the internal clock; and to perform frequency conversion control only in a logical circuit with the internal-to-external clock frequency ratio being N:1 or N:2 for the clocks, wherein the equipment comprises: a signal generator for supplying a common reference clock to itself and peripheral equipment and generating a reference sync signal from the reference clock to synchronize itself and the peripheral equipment; a signal generator for generating its internal clock from the reference clock; a signal generator for generating timing signals to control the timing of access to the external bus in accordance with an internal-to-peripheral clock frequency ratio; and a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with generated timing signals.

Abstract: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

Abstract: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

Abstract: A fault detecting apparatus includes first and second processors having an internal state generating logic unit for exclusive-ORing the operation outputs and generating an internal state signal of the first and second processors, and a state comparator unit included in the first and second processors for comparing the internal state signals of the first and second processors. When the internal state signals fail to coincide with each other, the state comparator unit decides on an error of at least one of the first and second processors.

Abstract: A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

Abstract: A virtual computer system having a translation lookaside buffer which converts a virtual address to a real address comprises a register (VMNR) for storing the identification number (VMID) of a currently running virtual machine, the translation lookaside buffer having a bit for holding the VMID and a comparison circuit which compares the VMID held in the bit with the VMID provided by the VMNR and predicates the success of conversion from a virtual address to a real address on the basis of a matching result of comparison, a management table for holding data indicative of VMIDs used to define virtual machines which have run up to the current time point, and a control circuit which, when an invalidation command for the translation lookaside buffer is issued during a run of a virtual machine, selects an unused VMID as first information for defining the running virtual machine on the basis of the contents of the management table and sets the selected VMID in the VMNR.

Abstract: An address translation apparatus is provided which has an address translation look-aside buffer with an entry composed of a real address field, virtual machine identifier field and space identifier field. For the translation look-aside buffer entry to be used by a general virtual machine which uses a plurality of address spaces, a virtual machine identifier for discrimination of a general virtual machine is stored in the virtual machine identifier field, and information used in discriminating an address space is stored in the space identifier field. For the translation look-aside buffer entry to be used by a dynamic address translation off (DATOFF virtual) machine which uses a single address space, an identifier commonly assigned to a group of DATOFF virtual machines is stored in the virtual machine identifier field, and a control block address used in discriminating a DATOFF virtual machine is stored in the space identifier field.