Abstract: An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Abstract: An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Abstract: In an image processing device, a lowpass filter extracts a low-frequency component of 8-bit input image data VI1 to obtain 10-bit image data LP1 expanded in the course of an operation during the extraction of the low-frequency component. Two less significant bits of the image data LP1 are rounded in a rounding circuit, and the obtained image data is output as 8-bit image data RD1. A comparator compares the image data RD1 with image data VI2, and an image output control circuit outputs a control signal OC1 based on a result CP1 of the comparison. A bit addition circuit adds 2 bits to the LSB of the image data VI1 to output 10-bit image data BS1. An output image selection circuit selects the image data LP2 or the image data BS2 based on the control signal OC1 to output as 10 bit-image data VO1.

Abstract: A digital signal receiver comprises a signal separating section (11), a clock signal generating section (12), a video data processing section (14), an audio data processing section (15), and a control section (17). The clock signal generating section (12) generates an operation clock signal (105) for the signal separating section (11), the video data processing section (14), and the audio data processing section (15). The control section (17) pauses the signal separating section (11), the video data processing section (14), and the audio data processing section (15) until receiving a clock stability signal (108) indicating that the operation clock signal (105) is stable, the clock stability signal (108) being generated by the clock signal generating section (12).

Abstract: An authentication processing apparatus includes an authentication unit, having a circuit that performs authentication phases included in processing for authenticating an external device. A command holding unit holds a first command that indicates whether or not each of the authentication phases is performed by the authentication unit. An authentication controller causes the authentication unit to perform an authentication phase that is indicated, by the first command, to be performed by the authentication unit. A CPU performs software processing of an authentication phase that is indicated, by the first command, not to be performed by the authentication unit.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: In a signal processing device, a first left eye noise extraction circuit and a first right eye noise extraction circuit perform the same noise extraction process. A second left eye noise extraction circuit and a second right eye noise extraction circuit perform different noise extraction processes. The signal processing control circuit controls a selector so that the selector selects the outputs of the left eye noise extraction circuits for a left eye video signal, and the outputs of the right eye noise extraction circuits for a right eye video signal. The correlation detection circuit detects a correlation between the left and right eye video signals, and controls a selector so that the selector selects the output of the first left or right eye noise extraction circuit when the correlation is high, and the output of the second left or right eye noise extraction circuit when the correlation is low.

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: In an audio and video transmission apparatus, a frequency division parameter control unit outputs a frequency division parameter Pt, Qt for relating a pixel clock (frequency: pclk) for video data with an audio clock (frequency: ft) for audio data. An audio/video/packet multiplexing unit converts audio data and the frequency division parameter Pt, Qt into packets, and superimposes the packets into blanking intervals of video data, thereby producing transmission data. The frequency division parameter Pt, Qt satisfies a relationship represented by: pclk/Pt=ft/Qt=fpt, and cause fpt to have a value that falls outside of a predetermined band that is determined as the band of audio data.

Abstract: A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising: input means for inputting AV data of a plurality of channels being transferred using a transport packet of a transport stream; a smaller number of PCR extracting means for extracting in a time-sharing mode the PCR of a plurality of channels displayed on said plurality of screens than the number of said plurality of screens; the same number of PLL means for establishing PLL synchronization by using said extracted PCR as the number of said plurality of screens; the same number of STC (system time clock) counter means for counting the times of the channels displayed on said plurality of screens by using the oscillation frequency of said PLL means as the number of said plurality of screens; AV decoding means for AV-decoding the AV data of the channels displayed on said multiscreen in AV synchronizati

Abstract: The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).

Abstract: A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.

Abstract: A transmitter 14, which receives an input video signal VS_IN and an input audio signal AS_IN from an MPEG decoder 17, includes therein a dummy signal production circuit 11 and a selection circuit 12. The dummy signal production circuit 11 produces a dummy video signal VS_D having a higher resolution than that of the input video signal VS_IN. The selection circuit 12 outputs one of the input video signal VS_IN and the dummy video signal VS_D as a selected video signal VS to a video/audio transmitter circuit 13, based on a control signal CS input based on an amount of information of the input audio signal AS_IN. The video/audio transmitter circuit 13 multiplexes the input audio signal AS_IN with the selected video signal VS to produce and transmit a video/audio signal VAS. Thus, irrespective of the format of the video signal, an audio signal having a high sample rate or a multi-channel audio signal can be transmitted while being multiplexed with the video signal.

Abstract: A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.