Patents by Inventor Ryohei Iida

Ryohei Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6473091
    Abstract: An image processing apparatus and method which can reduce the size of circuits for &agr;-blending and dithering and realize high speed processing which perform in parallel processing for finding an amount of update of present image data to be drawn with respect to image data already stored in a display buffer by using a blending coefficient in a subtractor and a multiplier and processing for adding noise data to the image data already stored in the display buffer in a first adder and adding the data obtained by the two processing at a second adder so as to find data comprised of noise data added to data obtained by linear interpolation of two colors, then extracting color valid values at a clamp circuit, thinning out the extracted data in a rounding-off circuit, and writing it back to the display buffer.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: October 29, 2002
    Assignee: Sony Corporation
    Inventors: Ryohei Iida, Takashi Takemoto
  • Patent number: 6373494
    Abstract: A signal processing apparatus for linear interpolation capable of performing operations to obtain suitable original data even when an interpolation coefficient &agr; is 1.0, wherein a correction term selects A when &agr;=0×FF (&agr;=1.0) and selects B when the bit is 0. The selected data becomes an element of addition by being shifted for the number of bits of &agr;. A product summation operation term uses the upper 8 bits of the result of multiplication of 8 bits×8 bits and shifts the 8-bit result of operation 8 bits to the left so as to enable further addition of the product summation operation term. An adder adds the shifted correction term, the partial products out—0 to out—7, and the product summation operation term and outputs the upper 8 bits as the result of the operation.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: April 16, 2002
    Assignee: Sony Corporation
    Inventors: Toshio Horioka, Ryohei Iida
  • Patent number: 6040844
    Abstract: A system for mapping texture data at high speed with flexibility to different applications wherein texture data is sent to a memory interface (MEMIF) thorough a digital differential analyzer (DDA) and a texture mapping unit (TMAP) and loaded to free areas of a Z coordinatory memory (ZBUF) and a drawing data memory (FBUF). A Z coordinate value or drawing data is read/written through a bidirectional port. The TMAP converts texture coordinates into a physical address, reads texture data from dedicated read ports of the ZBUF and the FBUF with the physical address, and maps the texture data. Each of the ZBUF and the FBUF has a DRAM unit and an auxiliary memory. Data of one row of the DRAM unit can be sent to the auxiliary memory means at a time. When desired texture data is not present in the auxiliary memory, data of the entire row of the desired texture data is sent to the auxiliary memory and then read.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: March 21, 2000
    Assignee: Sony Corporation
    Inventors: Yuji Yamaguchi, Masaharu Yoshimori, Hiroyuki Ozawa, Ryohei Iida, Kazuo Taniguchi