Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

Abstract: A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.A method of manufacturing a CMOS having such a MIS transistor decreases the number of the manufacturing steps because the double offset region of a first conductivity type channel MIS transistor and the offset region of a second conductivity type channel MIS transistor are simultaneously formed.

Abstract: A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.

Abstract: A first PSG film having a control hole is formed on a silicon substrate formed having a circuit, and a first aluminum alloy line layer resistive to stress migration made of Al-Si alloy is formed on the first PSG film, so as to electrically contact, via the contact hole, the surface of a semiconductor substrate. The alloy line layer is formed by use of a sputtering method, and the crystal face is oriented, mainly in the (111) plane, by controlling the substrate temperature at the time of sputtering, as well as the Ar gas pressure, the alloy depositing rate, and the degree of vacuum prior to the commencement of alloy depositing. The grain size l of the alloy crystal is set so as to satisfy "(W/14)<l<W" with respect to the width W of the line formed by etching, and preferably to also satisfy "(W/4)<l<(W/1.5)".