Abstract: A main processor sends to a command distribution device a series of graphic commands including an attribute command updating the state of the attribute which designates a display mode, and a primitive command defining graphics to be displayed. The command distribution device sequentially distributes the series of graphic commands to a plurality of geometry processors which process the graphics according to the type of command. The primitive command is sent to any one of plurality of geometry processors. At least those of the attribute commands which relate to the attributes of display used by the geometry processors are sent to all the geometry processors. The pixel commands comprising the outputs of those geometry processors are sent to a pixel processor which generates an image corresponding to the pixel commands.

Abstract: A semiconductor device having a memory array on a semiconductor chip includes an internal address producing circuit on the same semiconductor chip. The internal address producing circuit produces an internal address actually designating a memory cell or cells in the memory array according to an external address and a base address stored in a register formed on the semiconductor chip. The internal address produced by the producing circuit has a bit length longer than that of the external address.

Abstract: A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between adjacent layers of the hierarchy. The data processors are connected to a plurality of first layer serial bus loops and the I/O device which is commonly accessible by the data processors is connected to a second layer of serial bus loop. The interbus linkage devices control linkage among the plurality of serial bus loops and carry out routing control for a start command from the data processor to the I/O device, routing control for an interruption to report the end of I/O device operation, routing control for data transfer, routing control for a request interruption and exclusive use control of the shared I/O device.

Abstract: A memory device having initial set function for setting contents of memory cells at a predetermined state prior to data processing comprises a plurality of memory cells, at least one sense amplifier, at least one data line coupled between the sense amplifier and the memory cells and means for forcibly setting an output potential of the sense amplifier at a predetermined logic level.