Patents by Inventor Ryojiro Tominaga

Ryojiro Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945886
    Abstract: A cured resin formation method including an applying step of applying an ultraviolet curable resin on a base; and a curing step of curing the ultraviolet curable resin by irradiating the ultraviolet curable resin applied in the applying step with ultraviolet rays, in which in the curing step, the ultraviolet curable resin is irradiated with ultraviolet rays while cooling the ultraviolet curable resin, so that a difference between an ordinary temperature of the ultraviolet curable resin and a temperature of the ultraviolet curable resin when irradiated with ultraviolet rays is within a set temperature difference set in advance.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 2, 2024
    Assignee: FUJI CORPORATION
    Inventors: Tasuku Takeuchi, Ryojiro Tominaga
  • Publication number: 20240023249
    Abstract: A circuit forming method including a first wiring forming step of forming a first metal wiring on a resin layer, and a second wiring forming step of forming a second metal wiring on the first metal wiring, in which a Young's modulus of the first metal wiring and a Young's modulus of the second metal wiring are different from each other.
    Type: Application
    Filed: November 10, 2020
    Publication date: January 18, 2024
    Applicant: FUJI CORPORATION
    Inventors: Kenji TSUKADA, Ryojiro TOMINAGA
  • Publication number: 20230405935
    Abstract: To provide a production method and a production device for a three-dimensionally fabricated object that can alleviate a limitation on a curable resin to be used, in a case where the three-dimensionally fabricated object having an electronic device is produced using an additive manufacturing method. A production method for a three-dimensionally fabricated object of the present disclosure includes a first fabricating step of fabricating the attached object including an attachment section, to which the electronic device is attachable, with a first curable resin, using an additive manufacturing method, a second fabricating step of fabricating a resin layer with a second curable resin, fabricating a conductor with a fluid containing a metal particle, and fabricating the electronic device having the conductor in the resin layer, using the additive manufacturing method, and an attaching step of attaching the electronic device to the attachment section of the attached object.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 21, 2023
    Applicant: FUJI CORPORATION
    Inventor: Ryojiro TOMINAGA
  • Patent number: 11849545
    Abstract: A circuit formation method includes: a protruding portion formation step of forming a protruding portion by applying a curable viscous fluid onto a base and curing the curable viscous fluid; a wiring formation step of forming a wiring extending toward the protruding portion by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and making the metal-containing liquid conductive; a paste application step of applying a resin paste containing micrometer-sized metal particles different from the metal-containing liquid on the protruding portion and the wiring, such that the protruding portion and the wiring are connected to each other; and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied on the protruding portion.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 19, 2023
    Assignee: FUJI CORPORATION
    Inventors: Kenji Tsukada, Ryojiro Tominaga
  • Publication number: 20230112913
    Abstract: To provide a wiring formation method that can increase the wiring density in a case where wiring is formed on an inclined surface by three-dimensional additive manufacturing. The wiring formation method of the present disclosure includes a metal member forming step of forming multiple metal members with a first fluid containing metal particles, a resin layer forming step of forming a resin layer including an upper surface and an inclined surface inclined downward from the upper surface, and a connection wiring forming step of forming multiple connection wirings on the inclined surface and the upper surface of the resin layer with a second fluid containing metal particles, and the connection wirings being formed to individually connect the multiple connection wirings to the multiple metal members on a lower surface of the inclined surface.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 13, 2023
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Yoshitaka HASHIMOTO
  • Patent number: 11540397
    Abstract: A printed substrate forming method includes: a resin layer forming step of forming a resin layer with curable resin in a specific region that is a region other than a predetermined region of a base which is composed of an insulating layer and a conductor layer, the predetermined region of which being a region on which a solder resist is formed; and a wiring forming step of forming a wiring by discharging metal-containing liquid which contains metal fine particles onto a top surface of the resin layer, and firing the metal-containing liquid.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 27, 2022
    Assignee: FUJI CORPORATION
    Inventor: Ryojiro Tominaga
  • Publication number: 20220332052
    Abstract: An image processing device that processes an image in which a wiring pattern is drawn and outputs the image as raster data in which formation content of wiring print dots is defined for each pixel, includes an input section that receives the image, a scan section that sequentially performs scanning in a scan direction at intervals of the pixel width, a calculation section that calculates an intersection-to-intersection distance in the scan direction based on positions of the intersection points, and a determination section that determines a line width of the wire in the scan direction and determine formation of dots for the determined line width for each pixel based on the intersection-to-intersection distance, the prescribed width, and a line width of an inclination wire which is the line width, in the scan direction, of a wire inclined according to the prescribed angle.
    Type: Application
    Filed: September 24, 2019
    Publication date: October 20, 2022
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Akihiro KAWAJIRI
  • Patent number: 11458722
    Abstract: Disclosed is a method of manufacturing a three-dimensional multi-layer electronic device, the method including: a unit forming process of forming a multi-layer unit including an electronic component and a circuit wiring by three-dimensional lay-out forming; and a unit lay-out process of manufacturing a three-dimensional multi-layer electronic device by laying out and integrating the multi-layer unit in a vertical direction.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 4, 2022
    Assignee: FUJI CORPORATION
    Inventor: Ryojiro Tominaga
  • Publication number: 20220298267
    Abstract: A cured resin formation method including an applying step of applying an ultraviolet curable resin on a base; and a curing step of curing the ultraviolet curable resin by irradiating the ultraviolet curable resin applied in the applying step with ultraviolet rays, in which in the curing step, the ultraviolet curable resin is irradiated with ultraviolet rays while cooling the ultraviolet curable resin, so that a difference between an ordinary temperature of the ultraviolet curable resin and a temperature of the ultraviolet curable resin when irradiated with ultraviolet rays is within a set temperature difference set in advance.
    Type: Application
    Filed: July 31, 2019
    Publication date: September 22, 2022
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20220279658
    Abstract: In a case where a circuit wiring is formed on a resin member by three-dimensional additive manufacturing, a method for manufacturing the circuit wiring by three-dimensional additive manufacturing capable of suppressing swelling or cracking of the circuit wiring is provided. A method for manufacturing a circuit wiring by three-dimensional additive manufacturing includes a discharging step of discharging a fluid containing a metal particle onto a resin member formed of a resin material; and a circuit wiring forming step of forming a circuit wiring by heating the fluid containing the metal particle discharged onto the resin member at a heating temperature to be cured, and the heating being performed at the heating temperature based on a glass transition point of the resin material, a linear expansion coefficient of the resin material, and a room temperature.
    Type: Application
    Filed: July 31, 2019
    Publication date: September 1, 2022
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Ryo SAKAKIBARA, Tasuku TAKEUCHI, Yoshitaka HASHIMOTO, Kenji TSUKADA
  • Publication number: 20220279657
    Abstract: To provide an electronic circuit production method using 3D layer shaping capable of producing an electronic circuit having improved electrical properties and mechanical properties by utilizing characteristics of a fluid containing a metal particle by selectively using the fluid containing the metal particle. The electronic circuit production method using 3D layer shaping, the method including a wiring forming step of forming a wiring by applying a fluid containing a nano-sized metal nanoparticle on an insulating member and curing the applied fluid containing the metal nanoparticle; and a connection terminal forming step of forming a connection terminal electrically connected to the wiring by applying a fluid containing a micro-sized metal microparticle and curing the applied fluid containing the metal microparticle.
    Type: Application
    Filed: July 30, 2019
    Publication date: September 1, 2022
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Kenji TSUKADA, Ryo SAKAKIBARA, Tasuku TAKEUCHI
  • Publication number: 20220271010
    Abstract: In a method for manufacturing a stack component in which an interposer is interposed to form a space for inserting an interlayer connection pin between circuit layers to be stacked, the method includes a printing step of simultaneously printing and forming the circuit layer and the interposer side by side in a planar manner by a 3D printer, a step of mounting a circuit element on the circuit layer, a step of mounting the interposer on the circuit layer, a step of inserting the interlayer connection pin into the interposer mounted on the circuit layer, and a step of electrically connecting the circuit layer and another circuit layer by the interlayer connection pin by stacking the other circuit layer on the circuit layer via the interposer.
    Type: Application
    Filed: July 30, 2019
    Publication date: August 25, 2022
    Applicant: FUJI CORPORATION
    Inventor: Ryojiro TOMINAGA
  • Publication number: 20220264777
    Abstract: A three-dimensional molding machine for manufacturing a three-dimensional molded object comprising an electronic circuit includes multiple modules disposed adjacent to each other, a work unit provided in each of the multiple modules and configured to share a manufacturing operation for manufacturing the three-dimensional molded object on a pallet, and a pallet conveyance section provided in each of the multiple modules and configured to convey the pallet into and out of a module and to transfer the pallet between the module and another adjacent module of the multiple modules.
    Type: Application
    Filed: November 13, 2019
    Publication date: August 18, 2022
    Applicant: FUJI CORPORATION
    Inventors: Akihiro KAWAJIRI, Ryojiro TOMINAGA
  • Publication number: 20220240378
    Abstract: In multilayer circuit substrate wiring patterns and reference marks are formed on an upper surface of each insulating layer in a predetermined positional relationship, and the reference marks on the insulating layers are formed at overlapping positions when viewed from above. Furthermore, the reference mark on each layer is formed by changing a size or a shape such that from a specific edge portion recognized when center coordinates of the reference mark is detected by image processing a specific edge portion of the reference mark on a lower layer of the specific edge portion does not protrude considering a positional deviation at the time of manufacturing. The multiple insulating layers are formed of an insulating material having light transparency or an insulating material designed to be extremely thin so that a lower layer can be seen through even if the light transparency is poor.
    Type: Application
    Filed: June 13, 2019
    Publication date: July 28, 2022
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20220227043
    Abstract: A shaping method includes a first ejection step of ejecting a first curable viscous fluid, a planarization step of planarizing the first curable viscous fluid, a first curing step of curing the first curable viscous fluid, a cured layer forming step of repeatedly executing the first ejection step, the planarization step, and the first curing step to form a cured layer, a second ejection step of ejecting a second curable viscous fluid onto a surface of the cured layer, a second curing step of forming a smooth surface on the surface of the cured layer by curing the second curable viscous fluid, a third ejection step of ejecting a fluid containing metal particles onto the smooth surface, and a third curing step of curing the fluid containing the metal particles ejected in the third ejection step to form a metallic conductor on the smooth surface.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 21, 2022
    Applicant: FUJI CORPORATION
    Inventors: Kenji TSUKADA, Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20220039263
    Abstract: A circuit formation method includes: a protruding portion formation step of forming a protruding portion by applying a curable viscous fluid onto a base and curing the curable viscous fluid; a wiring formation step of forming a wiring extending toward the protruding portion by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and making the metal-containing liquid conductive; a paste application step of applying a resin paste containing micrometer-sized metal particles different from the metal-containing liquid on the protruding portion and the wiring, such that the protruding portion and the wiring are connected to each other; and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied on the protruding portion.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 3, 2022
    Applicant: FUJI CORPORATION
    Inventors: Kenji TSUKADA, Ryojiro TOMINAGA
  • Publication number: 20210267054
    Abstract: A circuit formation method includes a wiring formation step of forming a wiring by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and firing the metal-containing liquid, a paste application step of applying a resin paste containing micrometer-sized metal particles to be connected to the wiring formed in the wiring formation step, and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied in the paste application step.
    Type: Application
    Filed: July 13, 2018
    Publication date: August 26, 2021
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA, Ryo SAKAKIBARA
  • Publication number: 20210029832
    Abstract: A printed substrate forming method includes: a resin layer forming step of forming a resin layer with curable resin in a specific region that is a region other than a predetermined region of a base which is composed of an insulating layer and a conductor layer, the predetermined region of which being a region on which a solder resist is formed; and a wiring forming step of forming a wiring by discharging metal-containing liquid which contains metal fine particles onto a top surface of the resin layer, and firing the metal-containing liquid.
    Type: Application
    Filed: April 12, 2018
    Publication date: January 28, 2021
    Applicant: FUJI CORPORATION
    Inventor: Ryojiro TOMINAGA
  • Publication number: 20200346452
    Abstract: Disclosed is a method of manufacturing a three-dimensional multi-layer electronic device, the method including: a unit forming process of forming a multi-layer unit including an electronic component and a circuit wiring by three-dimensional lay-out forming; and a unit lay-out process of manufacturing a three-dimensional multi-layer electronic device by laying out and integrating the multi-layer unit in a vertical direction.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 5, 2020
    Applicant: FUJI CORPORATION
    Inventor: Ryojiro TOMINAGA
  • Patent number: 9832878
    Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 28, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Keisuke Shimizu, Makoto Terui, Ryojiro Tominaga, Yuichi Nakamura