Patents by Inventor Ryokichi Yoshizawa

Ryokichi Yoshizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6892261
    Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ohno, Tomoaki Nakamura, Shigenori Kaneko, Ryokichi Yoshizawa, Naoshi Kato, Manabu Yamauchi, Toshiaki Arai, Tomoki Sekiguchi
  • Publication number: 20040177193
    Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
    Type: Application
    Filed: February 10, 2004
    Publication date: September 9, 2004
    Inventors: Hiroshi Ohno, Tomoaki Nakamura, Shigenori Kaneko, Ryokichi Yoshizawa, Naoshi Kato, Manabu Yamauchi, Toshiaki Arai, Tomoki Sekiguchi
  • Patent number: 6715016
    Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ohno, Tomoaki Nakamura, Shigenori Kaneko, Ryokichi Yoshizawa, Naoshi Kato, Manabu Yamauchi, Toshiaki Arai, Tomoki Sekiguchi
  • Publication number: 20030154337
    Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 14, 2003
    Inventors: Hiroshi Ohno, Tomoaki Nakamura, Shigenori Kaneko, Ryokichi Yoshizawa, Naoshi Kato, Manabu Yamauchi, Toshiaki Arai, Tomoki Sekiguchi
  • Patent number: 5787464
    Abstract: A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: July 28, 1998
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Ryokichi Yoshizawa, Takeshi Miyao, Shigenori Kaneko, Tomoaki Nakamura, Hidebumi Miyata
  • Patent number: 5579508
    Abstract: A main memory managing arrangement involves allotting a request program to one of three distinct areas of main memory by looking in an area managing table which stores head addresses and the capacities of the respective areas. The areas allocated in main memory correspond to a single OS area, a single first class program area and a single second class program area. An empty page managing table is also provided for indicating the presence or absence of an empty area conformable to a request in an allocated area. A request program is allocated to the allocated area when the presence of the empty area of required capacity is determined. The memory capacity for a resident program can be assured independently of the memory capacities for other programs to enhance reliability conformable to real-time process computers.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: November 26, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Ryokichi Yoshizawa, Tomoaki Nakamura, Shigenori Kaneko