Patents by Inventor Ryosuke Kimoto
Ryosuke Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10595390Abstract: The plasma torch has a nozzle and body. The nozzle has an inner nozzle and inner cap fastened to the body with the inner nozzle. Annular water passage and a plurality of independent water passages are formed between the inner nozzle and inner cap. Force applied when the inner cap is fastened to the nozzle base is transmitted via partitions. The torch body has a water supply port and drain port. At least one of the water supply port and drain port is configured as a groove extending on a plane crossing the axis and is connected to the water passage. When the nozzle is fastened to the torch body, one of the independent water passages communicates with the water supply port and another communicates with the water drain port. Rear end surface of inner nozzle is in contact with end surface of the nozzle base thereby obtaining electrical conductivity.Type: GrantFiled: August 18, 2014Date of Patent: March 17, 2020Assignee: KOIKE SANSO KOGYO CO., LTD.Inventors: Ryosuke Kimoto, Masatoshi Motoyama, Tetsuya Iizuka, Susumu Kanda, Katsuhiko Sakamoto, Akira Hurujo, Daiji Sakai
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Publication number: 20160286637Abstract: [A problem to be solved] To provide a plasma torch in which a nozzle can be effectively cooled to an ejecting hole of plasm arc and which has a stable electrification properties [Measures to solve the problem] The plasma torch of the present invention has nozzle A and the torch body B. The nozzle A has the inner nozzle 2 and the inner cap 3 which is fastened to the torch body with the inner nozzle 2. The annular water passage 8 and a plurality of independent water passages 9 are formed between the inner nozzle 2 and the inner cap 3. A fastening force applied when the inner cap 3 is fastened to the nozzle base 14 is transmitted via the partitions 2f. The torch body B has the water supply port 20 and the water drain port 21. At least one of the water supply port 20 and the water drain port 21 is configured as a groove which extends on a plane which crosses the axis and which is connected to the water passage.Type: ApplicationFiled: August 18, 2014Publication date: September 29, 2016Applicant: Koike Sanso Kogyo Co., Ltd.Inventors: Ryosuke KIMOTO, Masatoshi MOTOYAMA, Tetsuya IIZUKA, Susumu KANDA, Katsuhiko SAKAMOTO, Akira HURUJO, Daiji SAKAI
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Publication number: 20130067424Abstract: A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction.Type: ApplicationFiled: August 23, 2012Publication date: March 14, 2013Inventors: Kenichi YAMAMOTO, Ryosuke Kimoto, Kenya Kawano, Hisashi Tanie, Yasuhiro Naka
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Patent number: 7420284Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: GrantFiled: July 25, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 7332800Abstract: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.Type: GrantFiled: June 4, 2004Date of Patent: February 19, 2008Assignee: Renesas Technology Corp.Inventors: Takashi Kikuchi, Ryosuke Kimoto, Hiroshi Kawakubo, Takashi Miwa, Chikako Imura, Takafumi Nishita, Hiroshi Koyama, Masanori Shibamoto, Masaru Kawakami
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Patent number: 7217645Abstract: Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.Type: GrantFiled: February 25, 2003Date of Patent: May 15, 2007Assignee: Hitachi, Ltd.Inventors: Shiro Yamashita, Masahide Harada, Kenichi Yamamoto, Munehiro Yamada, Ryosuke Kimoto
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Patent number: 7211892Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 ?m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10?3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.Type: GrantFiled: June 7, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Shiro Yamashita, Yoichi Abe, Kenichi Yamamoto, Ryosuke Kimoto, Hiroshi Kawakubo
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Publication number: 20060261494Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: July 25, 2006Publication date: November 23, 2006Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 7091620Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: GrantFiled: April 28, 2005Date of Patent: August 15, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Akita Electronics Systems, Co., Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Publication number: 20060151877Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 ?m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10?3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.Type: ApplicationFiled: June 7, 2005Publication date: July 13, 2006Inventors: Shiro Yamashita, Yoichi Abe, Kenichi Yamamoto, Ryosuke Kimoto, Hiroshi Kawakubo
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Publication number: 20050212142Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: April 28, 2005Publication date: September 29, 2005Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Publication number: 20050200019Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: April 28, 2005Publication date: September 15, 2005Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Patent number: 6879041Abstract: The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.Type: GrantFiled: March 26, 2003Date of Patent: April 12, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Yamamoto, Toshiaki Morita, Munehiro Yamada, Ryosuke Kimoto
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Publication number: 20050040509Abstract: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.Type: ApplicationFiled: June 4, 2004Publication date: February 24, 2005Inventors: Takashi Kikuchi, Ryosuke Kimoto, Hiroshi Kawakubo, Takashi Miwa, Chikako Imura, Takafumi Nishita, Hiroshi Koyama, Masanori Shibamoto, Masaru Kawakami
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Publication number: 20040061220Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: February 28, 2003Publication date: April 1, 2004Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Patent number: 6670215Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2002Date of Patent: December 30, 2003Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20030230806Abstract: Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.Type: ApplicationFiled: February 25, 2003Publication date: December 18, 2003Inventors: Shiro Yamashita, Masahide Harada, Kenichi Yamamoto, Munehiro Yamada, Ryosuke Kimoto
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Patent number: 6664135Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2002Date of Patent: December 16, 2003Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6642083Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2002Date of Patent: November 4, 2003Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems, Ltd., Hitachi ULSI Engineering Corp.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20030197277Abstract: The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.Type: ApplicationFiled: March 26, 2003Publication date: October 23, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Yamamoto, Toshiaki Morita, Munehiro Yamada, Ryosuke Kimoto