Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co); a first insulating layer provided between the semiconductor layer and the gate electrode layer; a charge storage layer provided between the first insulating layer and the gate electrode layer; a second insulating layer provided between the charge storage layer and the gate electrode layer; a third insulating layer provided between the second insulating layer and the gate electrode layer; and a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

Abstract: A semiconductor storage device includes: a plurality of conductive layers arranged in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage layer provided between the plurality of conductive layers and the semiconductor layer; a first structure disposed apart from the semiconductor layer in a second direction intersecting the first direction, extending in a third direction intersecting the first direction and the second direction, and facing the plurality of conductive layers; and a plurality of first nitride films containing nitrogen (N), and covering surfaces of the plurality of conductive layers facing the first structure.

Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.

Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, and a columnar portion. The stacked body, provided on the substrate, includes first conductive layers and first insulating layers provided alternately along a first direction. The columnar portion extends through the stacked body in the first direction. The columnar portion includes a blocking layer, a charge storage layer, a tunneling layer, and a semiconductor layer. The columnar portion includes a first portion and a second portion. The second portion is provided on the substrate side of the first portion. A dimension in the second direction of the second portion is smaller than a dimension in a second direction of the first portion. A portion of the blocking layer is provided at the second portion being thicker than a portion of the blocking layer provided at the first portion.

Abstract: A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, and a columnar portion. The stacked body, provided on the substrate, includes first conductive layers and first insulating layers provided alternately along a first direction. The columnar portion extends through the stacked body in the first direction. The columnar portion includes a blocking layer, a charge storage layer, a tunneling layer, and a semiconductor layer. The columnar portion includes a first portion and a second portion. The second portion is provided on the substrate side of the first portion. A dimension in the second direction of the second portion is smaller than a dimension in a second direction of the first portion. A portion of the blocking layer is provided at the second portion being thicker than a portion of the blocking layer provided at the first portion.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.

Abstract: A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.

Abstract: A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on a semiconductor substrate. An epitaxial layer is disposed on a surface of the semiconductor substrate and is electrically connected to a lower end of the semiconductor columnar portion. The semiconductor columnar portion comprises: an insulating film core; and a semiconductor portion disposed so as to cover a periphery of the insulating film core and electrically connected to the epitaxial layer at a lower end portion. The epitaxial layer includes a concave portion in a surface thereof, and the insulating film core has a lower end thereof positioned inside the concave portion.

Abstract: A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.