Patents by Inventor Ryota Suewaka
Ryota Suewaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220364260Abstract: Provided is a point detect simulator which makes it possible to determine the distribution of point defects in a silicon single crystal in consideration of the thermal stress of the silicon single crystal being grown. A point defect simulator 1 is a point defect simulator calculating the concentration profiles of vacancies and interstitial silicon during pulling of a silicon single crystal using a convection-diffusion equation reflecting the consideration of thermal stress in the silicon single crystal, and includes an analysis unit used to fit calculation results to experimental results using stress coefficients that are the coefficients of stress terms as a fitting parameter.Type: ApplicationFiled: August 12, 2020Publication date: November 17, 2022Applicant: SUMCO CORPORATIONInventor: Ryota SUEWAKA
-
Patent number: 11473210Abstract: Provided is a heat shielding member, a single crystal pulling apparatus, and a method of producing a single crystal silicon ingot, which can expand the margin of the crystal pulling rate with which a defect-free single crystal silicon can be obtained. A heat shielding member is provided in a single crystal pulling apparatus, the heat shielding member including a cylindrical tubular portion surrounding an outer circumferential surface of the single crystal silicon ingot; and a ring-shaped projecting portion under the tubular portion. The projecting portion has an upper wall, a bottom wall, and two vertical walls, a heat insulating material with a ring shape is provided in the space surrounded by those walls; and a gap between the vertical wall adjacent to the single crystal silicon ingot and the heat insulating material.Type: GrantFiled: March 16, 2018Date of Patent: October 18, 2022Assignee: SUMCO CORPORATIONInventors: Kaoru Kajiwara, Ryota Suewaka, Shunji Kuragaki, Kazumi Tanabe
-
Patent number: 10920339Abstract: A pulling condition calculation program enables a computer to perform the steps of: setting a plurality of sets of pulling conditions based on solid-liquid interface height and distance between a surface of a silicon melt and a heat shield plate; performing, for each set of the pulling conditions, the steps of: calculating a heat flux (q) (W/m2) and a crystal surface temperature (T); defining a reference temperature (Tref) given by an equation (1) below and a geometry of the solid-liquid interface as boundary conditions, recalculating an in-crystal temperature distribution; calculating a mean stress in the monocrystalline silicon; calculating a defect distribution in a pulling direction based on the mean stress and the in-crystal temperature distribution; determining a defect-free region in the pulling direction; and drawing a contour line showing a dimension of the defect-free region on a two-dimensional map defined by the distance and the solid-liquid interface height.Type: GrantFiled: December 7, 2017Date of Patent: February 16, 2021Assignee: SUMCO CORPORATIONInventor: Ryota Suewaka
-
Patent number: 10724150Abstract: A method of manufacturing a single crystal is provided with a raw material melting step of heating a silicon raw material in a quartz crucible using a carbon heater to generate a silicon melt; and a crystal pull-up step of pulling up a single crystal from the silicon melt generated by the raw material melting step, wherein the silicon raw material is heated with the maximum surface temperature of a first part of the heater that is positioned above at least the upper end of the quartz crucible maintained below 1500° C. in the raw material melting step.Type: GrantFiled: November 1, 2016Date of Patent: July 28, 2020Assignee: SUMCO CORPORATIONInventors: Kaoru Kajiwara, Ryota Suewaka, Hideki Tanaka, Takahiro Kanehara
-
Publication number: 20200224327Abstract: Provided is a heat shielding member, a single crystal pulling apparatus, and a method of producing a single crystal silicon ingot, which can expand the margin of the crystal pulling rate with which a defect-free single crystal silicon can be obtained. A heat shielding member is provided in a single crystal pulling apparatus, the heat shielding member including a cylindrical tubular portion surrounding an outer circumferential surface of the single crystal silicon ingot; and a ring-shaped projecting portion under the tubular portion. The projecting portion has an upper wall, a bottom wall, and two vertical walls, a heat insulating material with a ring shape is provided in the space surrounded by those walls; and a gap between the vertical wall adjacent to the single crystal silicon ingot and the heat insulating material.Type: ApplicationFiled: March 16, 2018Publication date: July 16, 2020Applicant: SUMCO CORPORATIONInventors: Kaoru KAJIWARA, Ryota SUEWAKA, Shunji KURAGAKI, Kazumi TANABE
-
Publication number: 20190330760Abstract: A pulling condition calculation program enables a computer to perform the steps of: setting a plurality of sets of pulling conditions based on solid-liquid interface height and distance between a surface of a silicon melt and a heat shield plate; performing, for each set of the pulling conditions, the steps of: calculating a heat flux (q) (W/m2) and a crystal surface temperature (T); defining a reference temperature (Tref) given by an equation (1) below and a geometry of the solid-liquid interface as boundary conditions,recalculating an in-crystal temperature distribution; calculating a mean stress in the monocrystalline silicon; calculating a defect distribution in a pulling direction based on the mean stress and the in-crystal temperature distribution; determining a defect-free region in the pulling direction; and drawing a contour line showing a dimension of the defect-free region on a two-dimensional map defined by the distance and the solid-liquid interface height.Type: ApplicationFiled: December 7, 2017Publication date: October 31, 2019Applicant: SUMCO CORPORATIONInventor: Ryota SUEWAKA
-
Publication number: 20180320288Abstract: A method of manufacturing a single crystal is provided with a raw material melting step of heating a silicon raw material in a quartz crucible using a carbon heater to generate a silicon melt; and a crystal pull-up step of pulling up a single crystal from the silicon melt generated by the raw material melting step, wherein the silicon raw material is heated with the maximum surface temperature of a first part of the heater that is positioned above at least the upper end of the quartz crucible maintained below 1500° C. in the raw material melting step.Type: ApplicationFiled: November 1, 2016Publication date: November 8, 2018Applicant: SUMCO CORPORATIONInventors: Kaoru KAJIWARA, Ryota SUEWAKA, Hideki TANAKA, Takahiro KANEHARA
-
Patent number: 8188529Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: January 7, 2009Date of Patent: May 29, 2012Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
-
Patent number: 7875116Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.Type: GrantFiled: February 14, 2006Date of Patent: January 25, 2011Assignee: Sumco Techxiv CorporationInventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
-
Publication number: 20090179246Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: ApplicationFiled: January 7, 2009Publication date: July 16, 2009Inventors: Yoshitaka NAKAMURA, Kenji KOMEDA, Ryota SUEWAKA, Noriaki IKEDA
-
Publication number: 20090061140Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.Type: ApplicationFiled: February 14, 2006Publication date: March 5, 2009Applicant: SUMCO TECHXIV KABUSHIKI KAISHAInventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
-
Publication number: 20070240629Abstract: The present invention relates to a method for manufacturing a silicon single crystal by pulling up the silicon single crystal from a molten silicon by the CZ method, comprising: a cooling step of cooling the silicon single crystal by a cooler surrounding the silicon single crystal, and a heat shield body disposed surrounding an outer side and a lower side of the cooler while the silicon single crystal is being pulled up; and an Ms adjusting step of determining, in advance, an allowable range of a pulling speed at which a silicon single crystal having few crystal defects can be obtained by adjusting a distance (referred to “Ms”) from the lower surface of the heat shield body disposed on the lower side of the cooler to the surface of the molten silicon, wherein the silicon single crystal 11 is pulled up at a pulling speed within the allowable range thus determined.Type: ApplicationFiled: April 10, 2007Publication date: October 18, 2007Inventors: Toshirou Kotooka, Takashi Yokoyama, Kazuyoshi Sakatani, Toshiaki Saishoji, Koichi Shimomura, Ryota Suewaka
-
Patent number: 7226506Abstract: A method for eliminating slip dislocations in producing single crystal silicon, a seed crystal capable of eliminating the slip dislocations, a single crystal silicon ingot from which the slip dislocations have been eliminated and a single crystal silicon wafer, are disclosed. Single crystal silicon is produced by dipping a seed crystal in a melt and pulling the seed crystal up along the axis of the seed crystal, using a single crystal (1) in which the <110> crystal orientation (10) is inclined at a predetermined angle ? with respect to the axial direction (9) so that the edge direction (8) of the {111} crystal plane is inclined with respect to the axial direction (9). When single crystal silicon is grown while pulling up a seed crystal by the CZ method, a single crystal silicon ingot of a large diameter and a heavy weight can be pulled up by eliminating slip dislocations from the thick crystal.Type: GrantFiled: April 17, 2003Date of Patent: June 5, 2007Assignee: Sumco Techxiv CorporationInventors: Tetsuhiro Iida, Yutaka Shiraishi, Ryota Suewaka, Junsuke Tomioka
-
Publication number: 20050229840Abstract: A method for eliminating slip dislocations in producing single crystal silicon, a seed crystal capable of eliminating the slip dislocations, a single crystal silicon ingot from which the slip dislocations have been eliminated and a single crystal silicon wafer, are disclosed. Single crystal silicon is produced by dipping a seed crystal in a melt and pulling the seed crystal up along the axis of the seed crystal, using a single crystal (1) in which the <110> crystal orientation (10) is inclined at a predetermined angle ? with respect to the axial direction (9) so that the edge direction (8) of the {111} crystal plane is inclined with respect to the axial direction (9). When single crystal silicon is grown while pulling up a seed crystal by the CZ method, a single crystal silicon ingot of a large diameter and a heavy weight can be pulled up by eliminating slip dislocations from the thick crystal.Type: ApplicationFiled: April 17, 2003Publication date: October 20, 2005Inventors: Tetsuhiro Iida, Yutaka Shiraishi, Ryota Suewaka, Junsuke Tomioka
-
Patent number: RE46882Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: November 12, 2014Date of Patent: May 29, 2018Assignee: Longitude Semiconductor S.a.r.l.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
-
Patent number: RE47988Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: May 28, 2018Date of Patent: May 12, 2020Assignee: Longitude Licensing LimitedInventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda