Abstract: A liquid crystal display element includes a pair of substrates, a liquid crystal layer sandwiched therebetween, gate lines and drain lines disposed to intersect the gate lines disposed on one of the substrates, thin film transistors disposed at the intersections of the gate and drain lines, pixel electrodes disposed in an area surrounded by two adjacent gate lines and two adjacent drain lines, a common electrode disposed on the other substrate. The liquid crystal display element is also provided with storage lines disposed below the pixel electrodes with an insulating layer interposed therebetween to form a capacitance therebetween. Each of the pixel electrodes is formed with an opening in a portion thereof facing the storage lines.

Abstract: Let drain driver output terminals (lead lines) be divided into six groups (R1, R2, G1, G2, B1, B2) of positive polarity and negative polarity for the three primary colors; bundle respective ones together for connection to drain line common lines; then, draw these drain line common lines out of a drain driver mount region; Let gate driver output terminals (lead lines) be divided into three groups (GA, GB, GC) of a front stage and next stage plus rear stage; bundle respective ones together for connection to gate line common lines; draw these gate line common lines out of a gate driver mount region; and then, perform tests with probes attached to test terminals provided at such drain line common lines and gate line common lines.

Abstract: A liquid crystal display element includes a pair of substrates, a liquid crystal layer sandwiched therebetween, gate lines and drain lines disposed to intersect the gate lines disposed on one of the substrates, thin film transistors disposed at the intersections of the gate and drain lines, pixel electrodes disposed in an area surrounded by two adjacent gate lines and two adjacent drain lines, a common electrode disposed on the other substrate. The liquid crystal display element is also provided with storage lines disposed below the pixel electrodes with an insulating layer interposed therebetween to form a capacitance therebetween. Each of the pixel electrodes is formed with an opening in a portion thereof facing the storage lines.