Abstract: In a distributed computing system, a master transmits a prepare request including a proposal number to a slave. When the proposal number included in the prepare request does not exist in management information, the slave sends back a prepare response including a new identifier associated with the proposal number to the master. The master transmits a write request including the identifier and a proposal to the slave. The slave writes the proposal into a memory area associated with the identifier included in the write request received from the master and, when writing is a success, sends back a write success response. The master determines that the slave having sent back the write success response has consented to the proposal.

Abstract: In a distributed computing system, a master transmits a prepare request including a proposal number to a slave. When the proposal number included in the prepare request does not exist in management information, the slave sends back a prepare response including a new identifier associated with the proposal number to the master. The master transmits a write request including the identifier and a proposal to the slave. The slave writes the proposal into a memory area associated with the identifier included in the write request received from the master and, when writing is a success, sends back a write success response. The master determines that the slave having sent back the write success response has consented to the proposal.

Abstract: In a GC processing in which a memory area is managed by being divided, collection efficiency of an area is further optimized. In order to realize the technology, a calculator including an arithmetic unit and a memory includes a storage unit which stores reference source information of data which is stored in a plurality of storage areas which are allocated to the memory in each of the storage areas; and a control unit which determines a storage area in which updated reference source information is different from reference source information which is recorded in the storage unit to be an area as a release target.

Abstract: Disclosed is a computer system for reliably running a plurality of programs performing garbage collection with less physical memory than in the past. For this purpose, there is disclosed a memory management method that releases unneeded areas in a plurality of memory areas that have been used by each of a plurality of programs stored in memory and executed on a processing unit, the processing unit acquires an index for determining the start of releasing a memory area, compares the index with a predetermined threshold, and when the index exceeds the threshold, selects one of the plurality of programs, collects unneeded areas of the memory areas used by the selected program, and releases the collected areas.

Abstract: A memory management method, which is used in a computer including a CPU and a memory to unload an area no longer necessary out of a memory area used by a program stored in the memory and executed by the CPU, comprising: generating a first processing system for executing the program in the memory; generating a second processing system in the memory when a first opportunity occurs; copying a content of a memory area of the first processing system to a memory area of the second processing system; determining an unnecessary area out of the copied memory area of the second processing system; transmitting a determination result regarding the unnecessary area to the program of the first processing system when a second opportunity occurs receiving the determination result; unloading the unnecessary area in the memory area of the first processing system.

Abstract: In a virtual machine system built from a plurality of virtual machines, the utilization efficiency of utilized physical memory is raised. A memory management method in which a virtual machine environment, constituted by having one or several virtual machines and a hypervisor part for operating the same virtual machines, is built on a physical machine and in which: a virtual machine operates an allocation processing part and an application part, application part making a physical memory processing part allocate unallocated physical memory to a memory area and allocation processing part transmitting, when unallocated physical memory is scarce, an instruction for the release, from memory areas utilized by each application part, of memory pages for which physical memory is assigned but not used.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen.

Abstract: A video display control system displays a video image composed of a plurality of display elements on a screen of a video display unit. The system comprises a memory (VRAM) for storing a plurality of color codes each representing at least one display element and a video display controller (VDP). The VDP comprises a mode register for selecting one of normal display and transparency processing modes, display processing circuit for reading the color codes from the VRAM, a backdrop color register for storing a color code such as one representing a backdrop color, a detection circuit for detecting a predetermined color code from the color codes read by the display processing circuit, and a selector controlled by an output of the detection circuit. In the normal display mode, the selector outputs all color codes read by the display processing circuit to the display unit.

Abstract: An improved display control system for use in a computer is disclosed which is equipped with functions of X, Y addressing and area movement so as to reduce the execution time necessary for display operations of the computer. Also, in this display control system, means for executing line commands is composed of the hardware so as to reduce the execution time necessary for display operations on the line commands.

Abstract: There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.

Abstract: A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data.

Abstract: A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM.

Abstract: A video display controller is provided with a color palette circuit which is capable of converting, at a high conversion rate, color codes read from a VRAM (video RAM) into RGB color data to be supplied to a CRT display unit. The color palette circuit comprises a plurality of color data registers each storing one RGB color data and is supplied with a timing signal synchronized with the display timing of display elements on the CRT display screen. Each color code data including at least two color codes and read from an address of the VRAM is first supplied to a selection circuit which includes at least two decoders. Each decoder decodes the corresponding color codes to generate a selection signal which enables one of the color data registers to output the RGB color data contained therein.

Abstract: A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data.

Abstract: A video display controller which can display foregrounds as well as backgrounds of display patterns on a screen of a video display unit in a plurality of colors. The video display controller comprises a plurality of color information registers, in each of which a pair of color code data representative of foreground and background colors of one display pattern are stored. A memory is provided for storing a plurality of pattern data, a plurality of pattern name data each designating one of the display patterns to be displayed on a respective one of display portions of the screen, and a plurality of color selection data each corresponding to a respective one of the display portions. A sequence controller sequentially reads the pattern data designated by the pattern name data and the color selection data in accordance with synchronization signals.

Abstract: A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus.