Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: A memory includes BLs and WLs. Resistance-change memory elements are connected between the BLs and the WLs via selection gates, respectively. A BL driver applies a voltage to a selected BL among the BLs. A WL driver applies a voltage to a selected WL among the WLs. In a write operation, the BL driver and the WL driver apply a first voltage between a reference voltage and a write voltage to selection candidate memory elements connected to the selected BL or the selected WL among the memory elements to bring the selection candidate memory elements to a half-selected state. The BL driver and the WL driver apply a second voltage to the selection candidate memory elements in the half-selected state at different timings, respectively, in order to bring the selection candidate memory elements to a write state and then return the selection candidate memory elements to the half-selected state.

Abstract: A semiconductor storage device according to an embodiment comprises a plurality of column power supply lines and a plurality of row power supply lines. A plurality of resistance-change memory cells are connected to the column power supply lines and the row power supply lines, respectively. A first column driver supplies a current to a first column power supply line among the column power supply lines. A second column driver supplies a current to a second column power supply line among the column power supply lines. In a data write operation, the first and second column drivers apply voltages having opposite polarities to the first and second column power supply lines, respectively. One of the first and second column drivers supplies a current to relevant ones of the memory cells and other thereof receives the current having passed through the memory cells.

Abstract: A semiconductor storage device according to an embodiment comprises a plurality of column power supply lines and a plurality of row power supply lines. A plurality of resistance-change memory cells are connected to the column power supply lines and the row power supply lines, respectively. A first column driver supplies a current to a first column power supply line among the column power supply lines. A second column driver supplies a current to a second column power supply line among the column power supply lines. In a data write operation, the first and second column drivers apply voltages having opposite polarities to the first and second column power supply lines, respectively. One of the first and second column drivers supplies a current to relevant ones of the memory cells and other thereof receives the current having passed through the memory cells.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to the storage elements, respectively. A voltage control circuit controls a decreasing rate of an absolute value of a voltage of a selected bit line among the bit lines when data is written to one of the storage elements.

Abstract: A memory includes BLs and WLs. Resistance-change memory elements are connected between the BLs and the WLs via selection gates, respectively. A BL driver applies a voltage to a selected BL among the BLs. A WL driver applies a voltage to a selected WL among the WLs. In a write operation, the BL driver and the WL driver apply a first voltage between a reference voltage and a write voltage to selection candidate memory elements connected to the selected BL or the selected WL among the memory elements to bring the selection candidate memory elements to a half-selected state. The BL driver and the WL driver apply a second voltage to the selection candidate memory elements in the half-selected state at different timings, respectively, in order to bring the selection candidate memory elements to a write state and then return the selection candidate memory elements to the half-selected state.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to the storage elements, respectively. A voltage control circuit controls a decreasing rate of an absolute value of a voltage of a selected bit line among the bit lines when data is written to one of the storage elements.

Abstract: A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data.

Abstract: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. First bit lines transmit read signal voltages from the memory cells. A gate of a first transistor is connected to the first bit lines. A second bit line is connected to one of a drain and a source of the first transistor. A step voltage line is connected to the other one of the drain and the source of the first transistor to apply a step voltage changing in a stepwise manner to the first transistor at a time of reading. A reference-voltage generator generates a reference voltage. A sense part is connected to the second bit line to receive the read signal voltages and the reference voltage.

Abstract: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. First bit lines transmit read signal voltages from the memory cells. A gate of a first transistor is connected to the first bit lines. A second bit line is connected to one of a drain and a source of the first transistor. A step voltage line is connected to the other one of the drain and the source of the first transistor to apply a step voltage changing in a stepwise manner to the first transistor at a time of reading. A reference-voltage generator generates a reference voltage. A sense part is connected to the second bit line to receive the read signal voltages and the reference voltage.

Abstract: A semiconductor storage device according to the present embodiment includes a constant current source. A reference current path is connected to the constant current source to flow a reference current and to generate a reference voltage. A supply current path or a plurality of supply current paths are connected to bit lines to selectively flow supply a current or currents different from each other and generate a detection voltage. A sense amplifier is connected to the reference current path and the supply current paths to amplify a voltage difference between the reference voltage and the detection voltage.

Abstract: A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data.

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value.

Abstract: A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.