Patents by Inventor Ryu Washino

Ryu Washino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142807
    Abstract: A semiconductor optical device includes: a buried layer having a side surface, an upper surface, and an intermediate region; an insulating film on the upper surface of the buried layer; and an electrode including a mesa electrode, a pad electrode, and a lead-out electrode. The upper surface of the buried layer has an outer edge including a first edge extending along the first direction and a second edge extending along a second direction. The intermediate region includes an upright surface that stands straight between the side surface and the first edge, and a slope surface that slopes more gently than the upright surface and extends downward from the second edge. The lead-out electrode includes a portion on the insulating film and connected to the pad electrode, another portion on the intermediate region and through the slope surface, and another portion connected to the mesa electrode.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 2, 2024
    Inventors: Ryu WASHINO, Yoshihiro NAKAI, Yuma ENDO, Saori HIZUME
  • Patent number: 11880098
    Abstract: A semiconductor optical device includes: a buried layer having a side surface, an upper surface, and an intermediate region; an insulating film on the upper surface of the buried layer; and an electrode including a mesa electrode, a pad electrode, and a lead-out electrode. The upper surface of the buried layer has an outer edge including a first edge extending along the first direction and a second edge extending along a second direction. The intermediate region includes an upright surface that stands straight between the side surface and the first edge, and a slope surface that slopes more gently than the upright surface and extends downward from the second edge. The lead-out electrode includes a portion on the insulating film and connected to the pad electrode, another portion on the intermediate region and through the slope surface, and another portion connected to the mesa electrode.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: January 23, 2024
    Assignee: Lumentum Japan, Inc.
    Inventors: Ryu Washino, Yoshihiro Nakai, Yuma Endo, Saori Hizume
  • Publication number: 20230280604
    Abstract: A semiconductor optical device includes: a buried layer having a side surface, an upper surface, and an intermediate region; an insulating film on the upper surface of the buried layer; and an electrode including a mesa electrode, a pad electrode, and a lead-out electrode. The upper surface of the buried layer has an outer edge including a first edge extending along the first direction and a second edge extending along a second direction. The intermediate region includes an upright surface that stands straight between the side surface and the first edge, and a slope surface that slopes more gently than the upright surface and extends downward from the second edge. The lead-out electrode includes a portion on the insulating film and connected to the pad electrode, another portion on the intermediate region and through the slope surface, and another portion connected to the mesa electrode.
    Type: Application
    Filed: June 29, 2022
    Publication date: September 7, 2023
    Inventors: Ryu WASHINO, Yoshihiro NAKAI, Yuma ENDO, Saori HIZUME
  • Patent number: 11705528
    Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 18, 2023
    Assignee: Lumentum Japan, Inc.
    Inventors: Ryu Washino, Hiroshi Hamada, Takafumi Taniguchi
  • Publication number: 20230155347
    Abstract: An optical semiconductor device includes a substrate, a semiconductor multilayer which is formed on the substrate, and includes an optical functional layer, an insulating film formed on the semiconductor multilayer, and an electrode formed on a part of the insulating film. The insulating film covers the semiconductor multilayer except for a region in which the semiconductor multilayer and the electrode are electrically connected to each other. At least a part of a region of the insulating film that is overlapped with the electrode is thinner than a region of the insulating film that is not overlapped with the electrode.
    Type: Application
    Filed: April 29, 2022
    Publication date: May 18, 2023
    Inventors: Atsushi NAKAMURA, Shigetaka HAMADA, Ryosuke NAKAJIMA, Ryu WASHINO, Shoko YOKOKAWA, Kouji NAKAHARA
  • Publication number: 20220166193
    Abstract: To provide an optical semiconductor device having excellent long-term reliability, the optical semiconductor device includes: a substrate; a mesa structure provided on the substrate; a semiconductor burial layer provided in contact with two sides of the mesa structure; and an electrode containing Au, which is provided above the semiconductor burial layer. The mesa structure includes a first conductivity type semiconductor layer, a multiple-quantum well layer, and a second conductivity type semiconductor layer, which are stacked in the stated order from a substrate side. The semiconductor burial layer includes a first semi-insulating InP layer provided in contact with side portions of the mesa structure, a first anti-diffusion layer provided in contact with the first semi-insulating InP layer, and a second semi-insulating InP layer provided on the first anti-diffusion layer. The first anti-diffusion layer has an Au diffusion constant that is smaller than that of the first semi-insulating InP layer.
    Type: Application
    Filed: June 22, 2021
    Publication date: May 26, 2022
    Inventors: Atsushi NAKAMURA, Hayato TAKITA, Shigetaka HAMADA, Ryosuke NAKAJIMA, Masatoshi ARASAWA, Ryu WASHINO
  • Publication number: 20210408303
    Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Ryu WASHINO, Hiroshi HAMADA, Takafumi TANIGUCHI
  • Patent number: 11121268
    Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: September 14, 2021
    Assignee: Lumentum Japan, Inc.
    Inventors: Ryu Washino, Hiroshi Hamada, Takafumi Taniguchi
  • Publication number: 20200357937
    Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.
    Type: Application
    Filed: April 9, 2020
    Publication date: November 12, 2020
    Inventors: Ryu WASHINO, Hiroshi HAMADA, Takafumi TANIGUCHI
  • Patent number: 9029970
    Abstract: Provided is a semiconductor light receiving device including: a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and including an upper surface portion; a reflecting film formed to cover the upper surface portion of the semiconductor layer and including a principal reflecting region and an upper surface; and an upper electrode formed to cover at least one portion of the upper surface of the reflecting film, and including a junction portion extending through the reflecting file to be provided in contact with the upper surface portion of the semiconductor layer, the junction portion of the upper electrode surrounding a portion of a circumference of the principal reflecting region of the reflecting film, the principal reflecting region being connected to a region of the reflecting film located outside the junction portion, in which the semiconductor light receiving device detects light entering from another side of the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 12, 2015
    Assignee: Oclaro Japan, Inc.
    Inventors: Ryu Washino, Yasushi Sakuma, Hiroshi Hamada
  • Publication number: 20110233708
    Abstract: Provided is a semiconductor light receiving device including: a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and including an upper surface portion; a reflecting film formed to cover the upper surface portion of the semiconductor layer and including a principal reflecting region and an upper surface; and an upper electrode formed to cover at least one portion of the upper surface of the reflecting film, and including a junction portion extending through the reflecting file to be provided in contact with the upper surface portion of the semiconductor layer, the junction portion of the upper electrode surrounding a portion of a circumference of the principal reflecting region of the reflecting film, the principal reflecting region being connected to a region of the reflecting film located outside the junction portion, in which the semiconductor light receiving device detects light entering from another side of the semiconductor substrate.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Inventors: Ryu WASHINO, Yasushi SAKUMA, Hiroshi HAMADA
  • Patent number: 7855093
    Abstract: A method of manufacturing semiconductor laser device capable of reducing ?L, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that each side wall has at least two or more crystal faces and a ratio of length of an upper side in a waveguide direction to a bottom side parallel to a (100) surface is 0 to 0.3. And, a reactive product formed on side surfaces of the diffraction grating and in trench portions between stripes of the diffraction grating at an increase of temperature for regrowth is removed. Therefore, the diffraction grating with reduced height and a sine wave shape is obtained, thereby ?L of the device is reduced. Thus, an oscillation threshold and optical output efficiency can be improved.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: December 21, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Kaoru Okamoto, Ryu Washino, Kazuhiro Komatsu, Yasushi Sakuma
  • Patent number: 7687295
    Abstract: In an optical semiconductor device that emits or receives light substantially perpendicularly to or in parallel to an active surface formed on a semiconductor substrate, the optical semiconductor device, an electrode that is formed on the active surface side and connected to the active surface is stepped or tapered at an end of the electrode. The electrode of the optical semiconductor device is formed of three layers including an adhesive layer, a diffusion prevention layer, and an Au layer, and the stepped configuration or the taped configuration is formed by a difference of the thickness of the Au layer or the thickness of the adhesive layer/diffusion prevention layer/Au layer.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: March 30, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Ryu Washino, Susumu Sorimachi, Daisuke Nakai, Kaoru Okamoto, Shigenori Hayakawa
  • Patent number: 7687874
    Abstract: In a mesa type PIN-PD formed using a heavily doped semiconductor material, a high frequency response is degraded as slow carriers occur in a heavily doped layer when light incident into a light receiving section transmits through an absorbing layer and reaches the heavily doped layer on a side near the substrate. In a p-i-n multilayer structure, a portion corresponding to a light receiving section of a heavily doped layer on a side near a substrate is previously made thinner than the periphery of the light receiving section by an etching or selective growth technique, over which an absorbing layer and another heavily doped layer are grown to form the light receiving section of mesa structure. This makes it possible to form a good ohmic contact and to realize a PIN-PD with excellent high frequency response characteristics.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 30, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Kazuhiro Komatsu, Yasushi Sakuma, Daisuke Nakai, Kaoru Okamoto, Ryu Washino
  • Publication number: 20100022043
    Abstract: A method of manufacturing semiconductor laser device capable of reducing ?L, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that each side wall has at least two or more crystal faces and a ratio of length of an upper side in a waveguide direction to a bottom side parallel to a (100) surface is 0 to 0.3. And, a reactive product formed on side surfaces of the diffraction grating and in trench portions between stripes of the diffraction grating at an increase of temperature for regrowth is removed. Therefore, the diffraction grating with reduced height and a sine wave shape is obtained, thereby ?L of the device is reduced. Thus, an oscillation threshold and optical output efficiency can be improved.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 28, 2010
    Applicant: OPNEXT JAPAN, INC.
    Inventors: Kaoru OKAMOTO, Ryu WASHINO, Kazuhiro KOMATSU, Yasushi SAKUMA
  • Patent number: 7459397
    Abstract: During the polishing of a semiconductor substrate, the semiconductor wafer that has been reduced in thickness, and hence in strength, by polishing, suffers outer-surface damage (or cracking) due to the initial damage caused by the use of polishing quartz. In order to solve these problems, the present invention applies a semiconductor substrate fixing jig formed with, on the face for fixing the semiconductor substrate, a groove(s) of almost the same diameter as that of the semiconductor substrate. Semiconductor substrate damage and cracking can be suppressed by applying this jig.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: December 2, 2008
    Assignee: OpNext Japan, Inc.
    Inventors: Ryu Washino, Yasushi Sakuma, Masaru Mukaikubo, Hura Harpreet Singh, Kenji Uchida
  • Publication number: 20080203404
    Abstract: In an optical semiconductor device that emits or receives light substantially perpendicularly to or in parallel to an active surface formed on a semiconductor substrate, the optical semiconductor device, an electrode that is formed on the active surface side and connected to the active surface is stepped or tapered at an end of the electrode. The electrode of the optical semiconductor device is formed of three layers including an adhesive layer, a diffusion prevention layer, and an Au layer, and the stepped configuration or the taped configuration is formed by a difference of the thickness of the Au layer or the thickness of the adhesive layer/diffusion prevention layer/Au layer.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 28, 2008
    Inventors: Ryu Washino, Susumu Sorimachi, Daisuke Nakai, Kaoru Okamoto, Shigenori Hayakawa
  • Publication number: 20080013582
    Abstract: A method of manufacturing semiconductor laser device capable of reducing ?L, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that each side wall has at least two or more crystal faces and a ratio of length of an upper side in a waveguide direction to a bottom side parallel to a (100) surface is 0 to 0.3. And, a reactive product formed on side surfaces of the diffraction grating and in trench portions between stripes of the diffraction grating at an increase of temperature for regrowth is removed. Therefore, the diffraction grating with reduced height and a sine wave shape is obtained, thereby ?L of the device is reduced. Thus, an oscillation threshold and optical output efficiency can be improved.
    Type: Application
    Filed: February 20, 2007
    Publication date: January 17, 2008
    Inventors: Kaoru Okamoto, Ryu Washino, Kazuhiro Komatsu, Yasushi Sakuma
  • Publication number: 20080006895
    Abstract: In a mesa type PIN-PD formed using a heavily doped semiconductor material, a high frequency response is degraded as slow carriers occur in a heavily doped layer when light incident into a light receiving section transmits through an absorbing layer and reaches the heavily doped layer on a side near the substrate. In a p-i-n multilayer structure, a portion corresponding to a light receiving section of a heavily doped layer on a side near a substrate is previously made thinner than the periphery of the light receiving section by an etching or selective growth technique, over which an absorbing layer and another heavily doped layer are grown to form the light receiving section of mesa structure. This makes it possible to form a good ohmic contact and to realize a PIN-PD with excellent high frequency response characteristics.
    Type: Application
    Filed: February 5, 2007
    Publication date: January 10, 2008
    Inventors: Kazuhiro Komatsu, Yasushi Sakuma, Daisuke Nakai, Kaoru Okamoto, Ryu Washino
  • Patent number: 7279349
    Abstract: In a dry etching step for an organic material film, a fluorine-containing member is disposed to the periphery of a semiconductor substrate disposed on a lower electrode or a tray for wafer transportation to form fluorine (fluoro-radicals) from the member per se in addition to the fluoric gas added to the etching gas, with a purpose of removing reaction products, thereby removing reaction products deposited on the semiconductor substrate efficiently and stably.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: October 9, 2007
    Assignee: OpNext Japan, Inc.
    Inventors: Yasushi Sakuma, Katsuya Motoda, Kenji Uchida, Ryu Washino