Patents by Inventor Ryuichi Oikawa
Ryuichi Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335513Abstract: The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit. Also, one-data-width distance is obtained by converting one-data-width interval, which is corresponding to a sampling period of an equalizer provided in one of the transmission unit and the receiving unit, to a distance. Further, a first reflection source for reflecting the signal is arranged at a position of the transmission line portion, where is corresponding to a ½-data-width distance corresponding to a half of the one-data-width distance. Here, the position corresponds to a grid point where a row grid line drawn on a screen used in the designing method and a column grid line drawn on the screen intersect with each other.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventor: Ryuichi OIKAWA
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Publication number: 20230335512Abstract: The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventors: Shuuichi KARIYAZAKI, Ryuichi OIKAWA
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Patent number: 11749597Abstract: A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.Type: GrantFiled: October 12, 2020Date of Patent: September 5, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 11437341Abstract: A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.Type: GrantFiled: December 1, 2020Date of Patent: September 6, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 11431378Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.Type: GrantFiled: December 6, 2019Date of Patent: August 30, 2022Assignee: Renesas Electronics CorporationInventor: Ryuichi Oikawa
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Publication number: 20220165672Abstract: A first semiconductor element (laser diode) and a second semiconductor element (laser diode) are connected to each other in series between a wiring electrically connected to an anode of the first semiconductor element and a wiring electrically connected to a cathode of the second semiconductor element. In this case, each of the first semiconductor element and the second semiconductor element includes a laminated pattern having an emission layer and a plurality of semiconductor layers covering this laminated pattern.Type: ApplicationFiled: November 3, 2021Publication date: May 26, 2022Inventor: Ryuichi OIKAWA
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Patent number: 11177235Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.Type: GrantFiled: December 31, 2019Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 11171083Abstract: By changing the characteristic impedance of the transmission line depending on the location, the transmission line functions as a band-pass filter.Type: GrantFiled: October 7, 2019Date of Patent: November 9, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 11171112Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.Type: GrantFiled: December 18, 2018Date of Patent: November 9, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Publication number: 20210233886Abstract: A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.Type: ApplicationFiled: December 1, 2020Publication date: July 29, 2021Inventor: Ryuichi OIKAWA
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Publication number: 20210159166Abstract: A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.Type: ApplicationFiled: October 12, 2020Publication date: May 27, 2021Inventor: Ryuichi OIKAWA
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Patent number: 10809470Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.Type: GrantFiled: May 13, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Tsuchiyama, Motoo Suwa, Ryuichi Oikawa
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Publication number: 20200235068Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.Type: ApplicationFiled: December 31, 2019Publication date: July 23, 2020Inventor: Ryuichi OIKAWA
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Publication number: 20200144177Abstract: By changing the characteristic impedance of the transmission line depending on the location, the transmission line functions as a band-pass filter.Type: ApplicationFiled: October 7, 2019Publication date: May 7, 2020Inventor: Ryuichi OIKAWA
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Publication number: 20200112335Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventor: Ryuichi OIKAWA
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Publication number: 20190377143Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.Type: ApplicationFiled: May 13, 2019Publication date: December 12, 2019Inventors: Kazuaki TSUCHIYAMA, Motoo SUWA, Ryuichi OIKAWA
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Patent number: 10403569Abstract: To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view.Type: GrantFiled: May 10, 2018Date of Patent: September 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Publication number: 20190229088Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.Type: ApplicationFiled: December 18, 2018Publication date: July 25, 2019Inventor: Ryuichi OIKAWA
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Patent number: 10347552Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.Type: GrantFiled: January 25, 2018Date of Patent: July 9, 2019Assignee: Renesas Electronics CorporationInventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
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Publication number: 20180374787Abstract: To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view.Type: ApplicationFiled: May 10, 2018Publication date: December 27, 2018Applicant: Renesas Electronics CorporationInventor: Ryuichi OIKAWA