Patents by Inventor Ryuichi Ujiie

Ryuichi Ujiie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8886141
    Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Nakane, Keisuke Kimura, Takaya Yamamoto, Tatsuji Matsuura, Ryuichi Ujiie
  • Patent number: 8686885
    Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuji Matsuura, Hideo Nakane, Masumi Kasahara, Ryuichi Ujiie, Keisuke Kimura, Oshima Takashi
  • Publication number: 20130249720
    Abstract: A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.
    Type: Application
    Filed: January 17, 2013
    Publication date: September 26, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuji Matsuura, Hideo Nakane, Masumi Kasahara, Ryuichi Ujiie, Keisuke Kimura, Oshima Takashi