Abstract: An operation apparatus includes signal lines, a decoder connected with the signal lines and configured to sequentially decode first and second instruction codes on the signal lines, an instruction executing section configured to execute operation processing based on each of the decoding results of the first and second instruction codes by the decoder, respectively, and an output unit connected with the signal lines and configured to continuously and sequentially output the first and second instruction codes onto the signal lines. Each of the first and second instruction codes comprises a first bit data and a second bit data. The first bit data of the first instruction code indicates that the first instruction code belongs to a first one of instruction code groups and at least a portion of the second bit data of the first instruction code indicates an instruction content of the first instruction code.

Abstract: In a single chip processor including an instruction ROM and a decoder for decoding instruction codes from the instruction ROM. During usual operation a multiplexer selects supplying instruction codes from the instruction ROM to the decoder. Alternatively, test instruction codes are input from an input interface via the multiplexer to the decoder in a test mode.

Abstract: In a semi-conductor integrated circuit device, a memory space provided with the integrated circuit device is not occupied by space for testing the integrated circuit device as the testing memory space. In the test mode of the semi-conductor integrated circuit device, test of internal circuit is capable of being implemented due to the fact that it permits a part of region belonging to the integrated circuit device to allocate to outer memory space. While in a normal operation mode, degree of freedom of design of the integrated circuit device is increased by releasing the testing memory space.

Abstract: A signal processor includes a normalization circuit (101, 102, 103, 106, 107, 108) for input data and a conversion table (110). A higher digit portion of mantissa portion after normalization is logarithmically converted by looking up table data stored in the conversion table (110). By shifting a decimal point position of the converted data, exponent data can be used as integer data and added to the converted data so that the conversion process is achieved.

Abstract: A circuitry with a pseudorandom noise generative function has a shift register for converting serial data into parallel data, an exclusive OR gate electrically connected to the shift register for fetching outputs from the shift register, the exclusive OR gate supplying exclusive ORed data to the shift register for use in generating a pseudorandom noise and a switch electrically connected to a data line transmitting serial digital data to be processed therein and an output of the exclusive OR gate for fetching the digital data and the exclusive ORed data respectively to select the serial digital data or the exclusive ORed data in response to a selective signal, the switch being electrically connected to the shift register for supplying the serial digital data or the exclusive ORed data to the shift register, thereby selecting a normal processing mode for the digital data or a pseudorandom noise generative mode for the exclusive ORed data.

Abstract: A break address detecting circuit sets a breakpoint in debugging a program for microprocessor, a signal processor, or the like. A first register holds a stop address ADstp. A first counter is initialized by a reset signal and counts up clock pulses in synchronism with a clock signal indicative of an instruction execution cycle. A selector selects a program address when the program is debugged, or selects output data from the first counter in step-by-step operation. A first comparator outputs a comparison result signal CR which is of an active level when output data from the selector and output data from the first register agree with each other. A second counter is initialized by the reset signal and counts up the comparison result signal each time the comparison result signal is of an active level. A second register holds a stop count CVstp. A second comparator outputs a break signal of an active level when output data from the second counter and output data from the second register agree with each other.

Abstract: A parallel multiplication circuit includes a plurality of Booth's decoders, a plurality of partial product generation circuits, and a plurality of full adders. Each Booth's decoder is constructed in accordance with the following decode signal generating logic:T.sub.w =Y.sub.i .sym.Y.sub.i-1P.sub.u =Y.sub.i+1Z=Y.sub.i+1 .sym.Y.sub.i .multidot.Y.sub.i .sym.Y.sub.i-1Each partial product generation circuit is constructed in accordance with the following partial product generating logic:PP=(T.sub.w .multidot.X.sub.i +T.sub.w .multidot.X.sub.i-1).sym.P.sub.

Abstract: This redundant binary type digital operation unit is provided with a redundant binary adder which gives a plurality of carry margin digits to the word length of the input redundant binary data on the higher digit side and further gives a protection digit for overflow judgment at the highest position to form the entire operation word length. It is also provided with a fixed value data output circuit to which a carry signal from the redundant binary adder showing whether a carry exists or not is input and which outputs the maximum value data when the carry signal value is "1" and the minimum value data when the carry signal value is a value other then "1", as well as a selection circuit which selects and outputs the output data from the redundant binary adder when the sign bit of the protection digit at the highest position sent from the redundant binary adder is "0", and the maximum or minimum value data from the fixed value data output circuit when the sign bit is "1".

Abstract: A serial data transmission circuit for performing a data transmission in a serial form includes a data shift signal input terminal, a data latch signal input terminal, and an output selector, the output of which is connected to a serial data output terminal. A shift register is connected at its serial input to a serial data input terminal and at a part of its parallel outputs to the input of the selector. A barrel shifter is provided, connected at its input to the parallel outputs of the shift register. The circuit further includes a first data latch, the input of which is connected to the output of the barrel shifter, and a second data latch, the output of which is connected to the parallel inputs of the shift register. The output of the first data latch is connected to the input of the second data latch through an internal data bus.

Abstract: Disclosed therein is an audio signal processing system for performing a balance control, which includes an attenuator for performing an amplitude attenuation operation on the designated channel signal and a delay circuit coupled in series to the attenuator for performing a phase delay operation on the designated channel signal. There is further provided a balance control unit which produces attenuation data and delay data in response to balance control information, the attenuation data and delay data being supplied to the attenuator and the delay circuit, respectively. Not only the amplitude but also phase of the designated channel signal are thereby attenuated and delayed.

Abstract: A disc control apparatus comprises a first register for storing a first track position which is presently traced, a second register for storing a second track position which is next to be traced, a first memory for storing a first rotating number of a disc under a seek operation, and a second memory for storing a second rotating number of the disc at a settling time. The first track position is an upper address signal for the first memory, and a lower address signal for the first memory is produced in accordance with a subtraction between the first and second track positions, so that the first memory is accessed at an address composed of the upper and lower addresses to produce the first rotating number signal. The second memory is accessed at an address determined solely by the first track position to produce the second rotating number signal.

Abstract: An overflow correction circuit is coupled to receive an output of an arithmetic operation circuit having first and second data inputs. The first data input is connected to an internal data bus so as to receive data to be subjected to an arithmetic operation, and the output of the arithmetic operation circuit outputs a result of arithmetic operation. The overflow correction circuit comprises a selector having a first input connected to receive the result of arithmetic operation from the arithmetic operation circuit and a second input and an output, a corrected value generating circuit having an output connected to the second input of the first selector, an overflow detection circuit coupled to receive the output of the arithmetic operation circuit and for generating an overflow signal indicative of whether or not there occurs an overflow in the result of the arithmetic operation.