Abstract: The invention provides a transcoder and a transcoding method capable of quickly transcoding video data of different compressive encoding schemes without increasing the circuit scale. A transcoder including a decoder (1), a syntax conversion section (2), and an encoder (3) is used. The decoder (1) decodes video data compressively encoded in accordance with the MPEG-2 scheme, extracts motion vectors produced in accordance with the MPEG-2 scheme, and performs dequantization on the video data other the motion vectors. The syntax conversion section (2) converts the syntax of the video data obtained from the decoder (1) to the H.264 scheme. The encoder (3) quantizes the video data obtained as a result of syntax conversion and compressively encodes it along with the extracted motion vectors in accordance with the H.264 scheme. The encoder (3) adds a descriptor indicating that the motion vectors have been produced in accordance with the MPEG-2 scheme to the obtained data.

Abstract: A unit with a built-in control circuit includes an outer housing and a control circuit package. The outer housing includes an electric wire holding part and receives the control circuit package. The control circuit package includes a lead frame, an IC chip, and a plastic molding body. The lead frame is made of conductive metal, and includes crimping terminals 20 and male tabs. The electric wire is press-fitted into the crimping terminal. The male tabs are connected to a mating connector. The IC chip is mounted on the lead frame. The plastic molding body covers and receives the IC chip and a center part of the lead frame.

Abstract: A connector includes a control circuit portion having a circuit element, and a housing which has a fitting portion which fits to a mating connector, a receiving chamber which receives the control circuit portion, and a wire holding portion which holds wires connected to the control circuit portion. The wire holding portion is provided on the opposite side of the fitting portion. The wire holding portion holds the wires so that the wires extend in a fitting direction in which the housing fits to the mating connector.

Abstract: A connector includes a control circuit portion having a circuit element, and a housing which has a fitting portion which fits to a mating connector, a receiving chamber which receives the control circuit portion, and a wire holding portion which holds wires connected to the control circuit portion. The wire holding portion is provided on the opposite side of the fitting portion. The wire holding portion holds the wires so that the wires extend in a fitting direction in which the housing fits to the mating connector.

Abstract: A unit with a built-in control circuit includes an outer housing and a control circuit package. The outer housing includes an electric wire holding part and receives the control circuit package. The control circuit package includes a lead frame, an IC chip, and a plastic molding body. The lead frame is made of conductive metal, and includes crimping terminals 20 and male tabs. The electric wire is press-fitted into the crimping terminal. The male tabs are connected to a mating connector. The IC chip is mounted on the lead frame. The plastic molding body covers and receives the IC chip and a center part of the lead frame.

Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

Abstract: A receiver to receive a mixture of progressive and interlace video broadcast signals without being conscious of switching between the broadcasting systems. The receiver receives the mixed video broadcast signals having different formats, converts received video signals to video signals having a different signal format from the signal format of the received video signals. The receiver simultaneously outputs the received video signals and the converted video signals. This allows the user to be unaware of any switching when the video input changes between the different broadcasting systems, by connecting a television set to either the interlace scanning system output or the progressive scanning system output of the receiver.

Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by means of the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

Abstract: A scan converting apparatus receives an NTSC signal which is scan converted and which has a changed aspect ratio. The subtitle domain, which is vertically overscaned out of the screen and cannot be observed, is extracted and superimposed on the scan converted image. Scanning lines of a brightness output signal of a brightness/chrominance signal separator are interpolated at a scanning line interpolator and are converted to a system which has more scanning lines at a scanning line converter. An odd/even field discriminator prevents deterioration of the resolution of the subtitle letters which is caused by an interchange of the positions between two adjacent scanning lines when the subtitle is transferred to a different field. By stopping the writing of data to a field memory in the subtitle signal processor when a subtitle is transferred, a subtitle transfer can be accomplished even when there is no subtitle on the image.

Abstract: The object of the present invention is to use signal decoding circuits for a first generation EDTV signal and a second generation EDTV signal in common and to suppress an increase of circuit scale.An EDTV signal decoding apparatus of the present invention is constructed with a cascade connection of a first A/D converter, a first signal processing circuit, a first D/A converter, a second A/D converter, a second signal processing circuit and a second D/A converter. The first group composed of the first A/D converter, the first signal processing circuit and the first D/A converter are driven by a clock signal synchronizing with a color burst signal. The second group composed of the second A/D converter, the second signal processing circuit and the second D/A converter are driven by a clock signal synchronizing with a horizontal sync signal.

Abstract: A scan converting apparatus receives an NTSC signal which is scan converted and which has a changed aspect ratio. The subtitle domain, which is vertically overscaned out of the screen and cannot be observed, is extracted and superimposed on the scan converted image. Scanning lines of a brightness output signal of a brightness/chrominance signal separator are interpolated at a scanning line interpolator and are converted to a system which has more scanning lines at a scanning line converter. An odd/even field discriminator prevents deterioration of the resolution of the subtitle letters which is caused by an interchange of the positions between two adjacent scanning lines when the subtitle is transferred to a different field. By stopping the writing of data to a field memory in the subtitle signal processor when a subtitle is transferred, a subtitle transfer can be accomplished even when there is no subtitle on the image.

Abstract: A double-picture type television receiver for displaying two different pictures on its screen. The television receiver is equipped with an image memory having a capacity required for storing a child picture signal to be inputted, the child picture signal to be stored being for one picture and a line memory coupled in series to an output of the image memory. Also included are multipliers, one being directly coupled to the output of the image memory for multiplying the output of the image memory by a predetermined coefficient and the other being coupled to outputs of the line memory for multiplying the outputs of the line memory by a predetermined coefficient. An adder calculates the sum of outputs of the multipliers and outputs the sum signal as a child picture signal.

Abstract: In an image display apparatus including a display unit for displaying an image of an inputted video signal thereon with a predetermined field frequency and a predetermined number of scanning lines using vertical and horizontal synchronizing signals for deflection of display in response to the inputted video signal, a first converter converts an inputted first video signal, having a first field frequency which is lower than the predetermined field frequency and having the predetermined number of scanning lines, into an output second video signal having the predetermined field frequency which is and the predetermined number of scanning lines, and having outputs the output second video signal to the display unit.

Abstract: An image signal magnifying apparatus is provided with a subtitle processing circuit capable of automatically detecting subtitles and moving the detected subtitle to a lower portion of a picture screen of an image display unit, when an image signal of a movie or the like, displayed on a picture screen having an aspect ratio of 4 to 3, is magnified to a picture screen having an aspect ratio of 16 to 9. Improvement of image quality of the characters of the subtitles after magnification of the image and simplification of the subtitle processing operation are attained. An output of a subtitle processing circuit 6 and an output of a number-of-scanning-line conversion circuit 9 are combined by a combining circuit 8.