Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming an active pattern on a substrate, forming a gate electrode traversing the active pattern on the active pattern, forming a recess adjacent to a sidewall of the gate electrode in the active pattern, and performing a chemical vapor deposition process using a source gas and a doping gas to form a source/drain region in the recess. The source gas may include a silicon precursor and a germanium precursor, and the doping gas may include a gallium precursor and a boron precursor.

Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.

Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.

Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.

Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.

Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during silicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during suicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.

Abstract: A clamp ring includes an abutting part abutting on the entire outer periphery of the main surface of a wafer when the wafer is fixed, and a brim part extending from the upper part of the abutting part to the inside of the wafer and provided so as not to abut on the main surface even when the wafer is fixed. The abutting part includes a first abutting section and a second abutting section, and a width of the first abutting section in a radial direction is greater than the width of the second abutting section in a radial direction.

Abstract: A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.

Abstract: A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.