Abstract: Disclosed is method of correcting code errors included in digital data that are structured in unit of frames, using first and second series of parity data. The method includes computing a first group of syndromes for the digital data using the first series of parity data. Then, a number of code errors included in the digital data is primarily decided based on the first group of syndromes, and the number of code errors included in the digital data is monitored in a frame by frame manner. In addition, the method includes primarily correcting at least one code error using the first group of syndromes and affixing an error flag to the digital data based on a result of monitoring the number of code errors. Then, a second group of syndromes for the digital data is generated using the second series of parity data.

Abstract: A semiconductor integrated circuit device has a first internal voltage controlling circuit which lowers an external power source voltage and produces a predetermined internal power source voltage. The device further has a second internal voltage controlling circuit formed by an internal-voltage drop detection circuit for detecting the lowering of the internal power source voltage from a predetermined reference voltage and a switching circuit for causing the external power source voltage to be directly connected to an internal voltage output terminal based on an output from the internal-voltage drop detection circuit. The internal power source voltage is maintained close to the required value thereby preventing a deterioration of circuit performance even when the external power source voltage drops close to the internal power source voltage.

Abstract: An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.

Abstract: A dynamic random access memory device includes a plurality of memory cell plates each having memory cells and a sense amplifier circuit array selectively coupled with the memory cells, and the sense amplifier circuit array selectively enters a standby mode and amplifying mode depending upon first and second driving signals supplied thereto, wherein the first and second driving signals are regulated to an intermediate voltage level between a step-down power voltage level and a ground voltage level in the standby mode with a main step-down power voltage signal supplied from a main step-down circuit; however, the first and second driving signals are changed to the step-down voltage level and the ground voltage level with an auxiliary step-down power voltage signal produced from an external power voltage signal at an auxiliary step-down circuit exclusively associated therewith so that undesirable voltage fluctuation hardly takes place on a main step-down power voltage line.

Abstract: An original layout pattern for reticle includes a tip pattern region, a scribe region formed around the tip pattern region, and alignment marks formed in the scribe region. Each end of the alignment marks is not reached to a edge of the original layout pattern. Therefore, when the original layout pattern is formed on the reticle side by side in predetermined times, the alignment marks positioned at an inner portion between two adjacent patterns are separated from each other.

Abstract: A semiconductor input protection device is disclosed which comprises a well type punch-through transistor consisting of a pair of parallel-opposed well layers through intermediation of a field oxide film, one of which is connected to an input terminal and the other to a reference potential. The device further comprises an impurity diffusion layer resistance with an end thereof connected to the input terminal. The lower limit distance between the opposed sides of the well layers to each other and the channel stopper is set to be smaller than that between the channel stopper and the input terminal-side well layer in the area where the latter and the impurity diffusion layer resistance intersect. The two lower limit distances depend on punch-through voltage, the width of the depletion layer in the well layer at applied punch-through voltage, and the junction disruptive strength of the well layer.

Abstract: A novel packing material suitable for high pressure liquid chromatography comprising the chemically bonded, crosslinked reaction product of porous inorganic particles, with an organic silane compound having epoxy groups on the surface of the particles, and then with polyvinyl alcohol, in which the hydroxyl groups of the polyvinyl alcohol and the epoxy groups on the silane moieties react to form ether bonds, which cover almost or almost completely the residual silica hydroxyl groups on the surface of the support.