Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Abstract: A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

Abstract: Herein disclosed are an amplifier and a display which uses the former. The amplifier includes a current amplifying circuit for sending out an amplified output current varying according to an input signal, and a current-voltage converting circuit for converting the output current of the current amplifying circuit into a voltage thereby to generate a high output voltage in response to the input signal. The supply voltage V.sub.cc1 of the current amplifying means and the supply voltage V.sub.cc2 of the current-voltage converting means are set separately of each other to have a relationship of V.sub.cc1 <V.sub.cc2. Thus, a high output voltage can be obtained from the current-voltage converting circuit without the need for the current amplifying means to have high breakdown voltage elements.

Abstract: Herein disclosed are an amplifier and a display which uses the former. The amplifier includes a current amplifying circuit for sending out an amplified output current varying according to an input signal, and a current-voltage converting circuit for converting the output current of the current amplifying circuit into a voltage thereby to generate a high output voltage in response to the input signal. The supply voltage V.sub.cc1 of the current amplifying means and the supply voltage V.sub.cc2 of the current-voltage converting means are set separately of each other to have a relationship of V.sub.cc1 <V.sub.cc2. Thus, a high output voltage can be obtained from the current-voltage converting circuit without the need for the current amplifying means to have high breakdown voltage elements.

Abstract: A camera having a microprocessor made receptive of various photographic informations through interrupt processing. The information at a higher priority level of said various photographic informations such as a release signal, a photometry start signal and a photometry introduction signal is fed to said microprocessor by the interrupting operation having a shorter period than that of the information at a lower priority level. The interrupt processing are periodic ones, and wherein an inequality of m<n holds when the information at the higher priority level of said various photographic informations is fed with a period m times as long as an interrupt period whereas the information at the lower priority level is fed with a period n times as long as said interrupt period.

Abstract: Battery voltage level warning is made according to the output signals of two detecting circuits. A first detecting circuit detects the power supply voltage having lowered to a value somewhat above the lower limit of the operation power supply voltage of an electronic system. The output thereof supplies weak battery warning. The second detecting circuit detects the power supply voltage having lowered to the lower limit level of said operation power-supply voltage. The output thereof prohibits the operation of said electronic system. Thereby, desirable battery-replacement times becomes clarified and the malfunction of said electronic system is prevented.

Abstract: A camera in which the automatic exposure control is conducted on the basis of measured light information obtained in accordance with the illumination of an object to be photographed. In the camera, a type of exposure control information that is predetermined irrespective of measured light information is supplied as first exposure control information into an exposure control circuit including an analog to digital converter. Subsequently, measured light information obtained through the operation of a shutter release of the camera is supplied thereinto as second exposure control information.

Abstract: The power supply resetting circuit of the invention is adapted to be used in such a type of camera that the shutter release action comprises two steps of strokes: a first stroke by which a power supply circuit for electric circuits mounted in the camera, such as a light measuring circuit, is closed, and a second stroke by which at least the operation of the circuits mounted in the camera is started. The power supply resetting circuit has a self-holding circuit for closing the power supply circuit and additionally mounted to the electric circuits in the camera. The self-holding circuit is adapted to be turned into operation by the second stroke of the shutter release action, substantially simultaneously with the starting of operation of the circuits mounted in the camera, and to be turned inoperative, so as to break the power supply circuit, at the instant at which the photographing sequence is completed or with a certain time lag to that instant.

Abstract: In a digital comparator wherein a period of time taken until one output signal of a decoder circuit coincides with one corresponding output signal of a frequency divider circuit is measured by comparing output signals of the decoder circuit and output signals of the frequency divider circuit, an output circuit of the decoder circuit and an output circuit of the frequency divider circuit are constructed of integrated injection logic (IIL) in order to build up wired AND circuits, and further, a NOR circuit which includes inverter circuits constructed of IIL and a common connection line for connecting outputs of the inverter circuits in common is disposed in order to receive respective outputs of the wired AND circuits. Especially, the digital comparator of this invention is effective for an automatic exposure control system of a camera.