Abstract: A data transfer device includes: a plurality of masters each having a buffer and configured to calculate a remaining-time counter based on an amount of data in the buffer; a memory system configured to perform data transfer with the plurality of masters and having a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter configured to arbitrate the plurality of masters based on the remaining-time counter; and a remaining-time counter-adjusting part configured to add a remaining-time counter offset, which adjusts the remaining-time counter until the start of the memory access prohibition period, to at least one of the plurality of masters.

Abstract: A data transfer device includes: a plurality of masters each having a buffer and configured to calculate a remaining-time counter based on an amount of data in the buffer; a memory system configured to perform data transfer with the plurality of masters and having a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter configured to arbitrate the plurality of masters based on the remaining-time counter; and a remaining-time counter-adjusting part configured to add a remaining-time counter offset, which adjusts the remaining-time counter until the start of the memory access prohibition period, to at least one of the plurality of masters.

Abstract: A defect pixel correction apparatus includes an internal memory which associates and stores a position of a defect pixel with an order of the defect pixel in an image sensor and a processor which corrects a pixel signal of an object pixel based on a pixel signal of an adjacent normal pixel when the adjacent normal pixel is present in the neighborhood of the object pixel and corrects the pixel signal of the object pixel based on a pixel signal of an adjacent defect pixel of a lowest order when the adjacent normal pixel is not present and the adjacent defect pixel of a lower order than an order of the object pixel is present.

Abstract: A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

Abstract: A defect pixel correction apparatus includes an internal memory which associates and stores a position of a defect pixel with an order of the defect pixel in an image sensor and a processor which corrects a pixel signal of an object pixel based on a pixel signal of an adjacent normal pixel when the adjacent normal pixel is present in the neighborhood of the object pixel and corrects the pixel signal of the object pixel based on a pixel signal of an adjacent defect pixel of a lowest order when the adjacent normal pixel is not present and the adjacent defect pixel of a lower order than an order of the object pixel is present.

Abstract: A display control device, includes a plurality of image data-processing units acquiring and outputting image data; a synchronous signal generation unit generating and outputting a synchronous signal to a first image data-processing unit; a delay adjustment unit delaying first image data output from the first image data-processing unit for each line; a filter-processing unit performing a product-sum operation of a filter coefficient and a first partial image data; and a display image generation unit generating display image data by superimposing the filter-processing data on second image data, wherein the synchronous signal is a vertical synchronous signal included in each frame, the synchronous signal generation unit controls whether to output the synchronous signal to the first image data-processing unit earlier by a predetermined offset time, and the offset time corresponds to the number of taps and a line cycle and is within a range net exceeding a vertical retrace period.

Abstract: A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

Abstract: The present invention provides a display processing device for superimposing a superimposed image for displaying additional information on a display image on the basis of transparency information when each pixel is displayed and causing the superimposed image superimposed on the display image to be displayed.

Abstract: A display control device, includes a plurality of image data-processing units acquiring and outputting image data; a synchronous signal generation unit generating and outputting asynchronous signal to a first image data-processing unit; a delay adjustment unit delaying first image data output from the first image data-processing unit for each line; a filter-processing unit performing a product-sum operation of a filter coefficient and a first partial image data; and a display image generation unit generating display image data by superimposing the filter-processing data on second image data, wherein the synchronous signal is a vertical synchronous signal included in each frame, the synchronous signal generation unit controls whether to output the synchronous signal to the first image data-processing unit earlier by a predetermined offset time, and the offset time corresponds to the number of taps and a line cycle and is within a range net exceeding a vertical retrace period.

Abstract: An image processing device includes a shooting scene determining section that determines a shooting scene, a correlation evaluation value calculating section that calculates correlation evaluation values between a target pixel and surrounding pixels, a weight setting section that sets, when the shooting scene is a low correlation scene, heavy weights to the correlation evaluation value calculated from the surrounding pixels having high correlativities, an isolated-point degree calculating section that subjects the correlation evaluation values to weight addition to calculate an isolated-point degree, and an FPN correcting section that corrects a pixel value of the target pixel according to a magnitude of the isolated-point degree correction.

Abstract: A display processing device includes: a first display processing unit that divides a display image into a first area and a second area and outputs a first output image obtained by performing display processing on display image data of the first area; a second display processing unit that outputs a second output image obtained by performing the display processing on display image data of the second area; a storage unit that temporarily stores the first and second output images; a memory writing control unit that controls writing of the first and second output images to the storage unit; an output selection unit that reads the first and second output images stored in the storage unit and outputs the read first and second output images to a first display device that displays a display image; and a clock control unit that supplies an operation clock to each element.

Abstract: A display processing device includes: a first display processing unit that outputs image data of a first output image obtained by performing display processing on display image data of an odd column of a display image; a second display processing unit that outputs image data of a second output image obtained by performing the display processing on display image data of an even column of the display image; an output selection unit that selects the image data of the first output image or the image data of the second output image and outputs the selected image data to a first display device that displays a display image; and a clock control unit that supplies an operation clock required when the respective elements operate.

Abstract: An image output apparatus includes a first synthesis processing unit configured to generate a first synthetic image for display through a synthesis process and output the first synthetic image, a second synthesis processing unit configured to generate a second synthetic image for synthesis through a synthesis process and cause the second synthetic image to be stored in the external storage area, and an image selection control unit configured to instruct the second synthesis processing unit to generate the second synthetic image, select whether or not the second synthetic image is to be used as one of the input images used to generate the first synthetic image, and instruct the first synthesis processing unit to generate the first synthetic image including the plurality of selected input images.

Abstract: An image processing device includes: a common region sum of absolute differences (SAD) calculation unit configured to define each of a common target region in which a plurality of target regions predetermined for each target pixel overlap and a common reference region in which a plurality of reference regions predetermined for each corresponding reference pixel overlap and output a common SAD calculation result obtained by performing SAD calculation based on values represented by pixel signals of pixels included in the common target region and the common reference region; and addition processing units equal in number to the target pixels to be simultaneously correlated and configured to correspond to the target pixels and output SAD calculation results obtained by performing addition processes based on the common SAD calculation result and an SAD calculation result of a region which is not included in the common target region within a target region.

Abstract: An image processing device includes a shooting scene determining section that determines a shooting scene, a correlation evaluation value calculating section that calculates correlation evaluation values between a target pixel and surrounding pixels, a weight setting section that sets, when the shooting scene is a low correlation scene, heavy weights to the correlation evaluation value calculated from the surrounding pixels having high correlativities, an isolated-point degree calculating section that subjects the correlation evaluation values to weight addition to calculate an isolated-point degree, and an FPN correcting section that corrects a pixel value of the target pixel according to a magnitude of the isolated-point degree correction.

Abstract: An image processing device includes an extended region sum of absolute differences (SAD) calculation unit configured to define each of an extended target region obtained by combining a plurality of predetermined target regions for each target pixel and an extended reference region obtained by combining a plurality of predetermined reference regions for each corresponding reference pixel and output an extended SAD calculation result obtained by performing SAD calculation based on values represented by pixel signals of pixels included in the extended target region and the extended reference region, and subtraction processing units equal in number to the target pixels to be simultaneously correlated and configured to correspond to the plurality of target pixels and output SAD calculation results obtained by performing subtraction processes based on the extended SAD calculation result and an SAD calculation result of a region which is not included in a target region.

Abstract: A display processing device includes: a first display processing unit that outputs image data of a first output image obtained by performing display processing on display image data of an odd column of a display image; a second display processing unit that outputs image data of a second output image obtained by performing the display processing on display image data of an even column of the display image; an output selection unit that selects the image data of the first output image or the image data of the second output image and outputs the selected image data to a first display device that displays a display image; and a clock control unit that supplies an operation clock required when the respective elements operate.

Abstract: A display processing device includes: a first display processing unit that divides a display image into a first area and a second area and outputs a first output image obtained by performing display processing on display image data of the first area; a second display processing unit that outputs a second output image obtained by performing the display processing on display image data of the second area; a storage unit that temporarily stores the first and second output images; a memory writing control unit that controls writing of the first and second output images to the storage unit; an output selection unit that reads the first and second output images stored in the storage unit and outputs the read first and second output images to a first display device that displays a display image; and a clock control unit that supplies an operation clock to each element.

Abstract: An image processing apparatus includes a buffer unit which stores image data of one input image, an input control unit which causes the buffer unit to store the image data of the input image, a processing operation unit which outputs image data of a processed image generated by performing image processing based on one of a plurality of set processing conditions, a plurality of output control units corresponding to the processing conditions, wherein each output control unit causes the image data necessary when image processing is performed in a corresponding processing condition to be output from the buffer unit to the processing operation unit and causes the image data of the processed image to be output to a subsequent-stage processing circuit, and an output arbitrating unit which determines which processing condition is used to perform the image processing and permits the corresponding output control unit to perform output control.

Abstract: An image processing device includes: a common region sum of absolute differences (SAD) calculation unit configured to define each of a common target region in which a plurality of target regions predetermined for each target pixel overlap and a common reference region in which a plurality of reference regions predetermined for each corresponding reference pixel overlap and output a common SAD calculation result obtained by performing SAD calculation based on values represented by pixel signals of pixels included in the common target region and the common reference region; and addition processing units equal in number to the target pixels to be simultaneously correlated and configured to correspond to the target pixels and output SAD calculation results obtained by performing addition processes based on the common SAD calculation result and an SAD calculation result of a region which is not included in the common target region within a target region.