Abstract: An image recognition system for detecting and tracking at least an image portion associated with a predefined object from a moving picture is configured to be able to perform: an object detection processing step of detecting the object; a tracking point specification processing step of specifying a predetermined point as a tracking point; a tracking target recognition processing step of recognizing an actual tracking target based on the tracking point; a tracking processing step of tracking the tracking target; and a determination processing step of determining the type of the tracking target's behavior. The tracking point specification processing step and the determination processing step are implemented by software, while the object detection processing step, the tracking target recognition processing step, and the tracking processing step are implemented by hardware.

Abstract: An image recognition system for detecting and tracking at least an image portion associated with a predefined object from a moving picture is configured to be able to perform: an object detection processing step of detecting the object; a tracking point specification processing step of specifying a predetermined point as a tracking point; a tracking target recognition processing step of recognizing an actual tracking target based on the tracking point; a tracking processing step of tracking the tracking target; and a determination processing step of determining the type of the tracking target's behavior. The tracking point specification processing step and the determination processing step are implemented by software, while the object detection processing step, the tracking target recognition processing step, and the tracking processing step are implemented by hardware.

Abstract: A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.

Abstract: A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.

Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

Abstract: An access control apparatus receives access requests from one or more regular masters and an irregular master and sequentially selects an access allowable target. Additionally, the access control apparatus calculates an amount of unused resources based on an amount of resources used by a regular master and a maximum amount of resources to be used by the regular master, and manages the unused resources. The access control apparatus selects an access request of an irregular master as an access allowable target when the irregular master makes the access request during a unit period and access based on an access request of at least one of the regular masters that has not been executed. The managed amount of unused resources is equal to or larger than an amount of resources which is to be used based on the access request of the irregular master.

Abstract: A cache memory and method for controlling the cache memory. The cache memory selects, from an access address, a unique set from among a plurality of sets, each access set including a plurality of cache entries. Each cache entry holds unit data for caching. The cache memory holds, for each of the cache entries, order data that indicates an access order of the cache entries in each set, and replaces a cache entry that is oldest in the access order. The cache memory modifies the order data regardless of an actual access order, and selects, based on the modified order data, a cache entry to be replaced.

Abstract: A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.

Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

Abstract: In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.

Abstract: The present invention aims to provide an access control apparatus that can improve responsiveness to an access request of a processor compared with a conventional technology. The access control apparatus, which receives access requests from one or more regular masters and a irregular master and sequentially selects an access allowable target, calculates an amount of unused resources based on an amount of resources used by a regular master which makes an access request during a unit period and a maximum amount of resources to be used given to the regular master and manages it.

Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

Abstract: In a device in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. In a case that the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.

Abstract: The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit 39 which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.

Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Abstract: The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

Abstract: The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.

Abstract: Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU0 and PU1 each of which issues an access request for accessing the shared memory, a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.