Patents by Inventor Sébastien Daveau

Sébastien Daveau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integration
    Patent number: 11973130
    Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the f
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 30, 2024
    Assignee: X-FAB FRANCE SAS
    Inventors: Sébastien Daveau, Sotirios Athanasiou
  • Method of Forming Asymmetric Differential Spacers for Optimized MOSFET Performance and Optimized MOSFET and SONOS Co-Integration
    Publication number: 20210234024
    Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the f
    Type: Application
    Filed: January 27, 2021
    Publication date: July 29, 2021
    Inventors: Sébastien Daveau, Sotirios Athanasiou