Patents by Inventor S. Gabriel R. Dosdos

S. Gabriel R. Dosdos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8362609
    Abstract: An integrated circuit package is described. The integrated circuit package comprises a substrate having a plurality of sides, where each pair of adjacent sides forms a corner; a die coupled to a first surface of the substrate; a lid having a first portion positioned over the die and a plurality of foot portions, each foot portion of the plurality of foot portions being coupled to the first surface of the substrate at a corresponding corner of the substrate, where a side of the integrated circuit package above the substrate and between two associated foot portions has an opening; and a plurality of contact elements coupled to a second surface of the substrate. A method of forming an integrated circuit package is also shown.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: January 29, 2013
    Assignee: Xilinx, Inc.
    Inventors: S. Gabriel R. Dosdos, Dong Wook Kim
  • Patent number: 8258013
    Abstract: An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 4, 2012
    Assignee: Xilinx, Inc.
    Inventors: Kumar Nagarajan, S. Gabriel R. Dosdos, Dong W. Kim, Kong W. Lee
  • Patent number: 6768329
    Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed form necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: July 27, 2004
    Assignee: Xilinx Inc.
    Inventors: S. Gabriel R. Dosdos, Joel J. Orona, Daniel C. Nuez
  • Patent number: 6433360
    Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed from necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: August 13, 2002
    Assignee: Xilinx, Inc.
    Inventors: S. Gabriel R. Dosdos, Joel J. Orona, Daniel C. Nuez