Abstract: In a DRAM, a logic "1" is redefined as the minimum VCC value minus one threshold voltage. The word line is not bootstrapped. This intermediate voltage is applied via the sense amplifier to the bit lines during refresh. The intermediate value is controlled preferably by a comparator controlling a driver. Even when the power supply voltage rises, the intermediate voltage is held constant by comparison to a fixed reference voltage. Operating current is substantially reduced because less power is required to write data into the memory cells, since a controlled lower voltage is used.

Abstract: In an output circuit for an integrated circuit memory, the current drawn by output transistors is lower at high V.sub.CC voltage range than at nominal V.sub.CC. Maximum current is drawn at the low end of the V.sub.CC voltage range.

Abstract: A supply circuit providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors which operate as a load to develop a voltage at first and second nodes. The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor, and to the gate electrode of a drive transistor and a third transistor. The drive transistor selectively couples operating voltage to the hold line. After the logic circuit turns off, the offset voltage which has been stored on the capacitor controls the drive transistor to couple the target holding voltage to the holding line.

Abstract: A constant current power supply circuit for an integrated circuit memory which is well suited for driving a high capacitance load, such as a large number of sense amplifiers. A first circuit provides a constant current source and a second "current mirror" circuit provides an output current proportionate to the first circuit, but at a higher desired level of current. The constant current circuit is achieved using two cross-coupled FET transistors and two resistances such that the conductivity of each transistor is inversely related to the conductivity of the other. The circuit reaches a constant current equilibrium which is largely independent of operating voltage or load, but rather depends on the relative values of the components.

Abstract: A voltage reference generated for an integrated circuit which produces a source of reference voltage which is self-compensated for variations in operating voltage (V.sub.cc) or in transistor threshold voltages (V.sub.T). The circuit uses a voltage divider coupled between V.sub.cc and ground and has first and second FET transistors. A faced control circuit is coupled to control the conductivity of the first transistor, and the second control circuit is coupled to control the conductivity of the second transistor. The first control circuit produces a control voltage which varies as a function of variations in V.sub.cc, while the second control circuit also provides a control voltage wherein variations are a function of variations in V.sub.cc, but in an opposite direction. Hence, the second control voltage is configured so that variations in V.sub.cc cause the second transistor to compensate for changes in operation of the first transistor, so that the reference voltage remains substantially constant.

Abstract: An improved DRAM memory cell uses ferroelectric material as the dielectric between capacitor plates. Preferably polycrystalline PZT or a perovskite is used for the ferroelectric, and the polar axes of the dipoles in the ferroelectric material in relaxed position are not aligned with the direction of the resulting electric field when voltage is applied to the capacitor plates. Preferably, the dipole orientation is in the plane of the ferroelectric film so that when a write voltage is removed from the capacitor plate, the dipoles tend to relax to a non-aligned position. When the cell is read or refreshed, increased charge is drawn from the bit line and resides on the capacitor plate in order to reorient the relaxed dipoles. The charge developed on the plate hence is magnified.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

Abstract: A semiconductor memory uses cells with a ferroelectric capacitor having one plate coupled to a bit line by a FET and another plate coupled to a plate line. A pulse on the plate line causes the bit line to change voltage based on the state of the cell. A dummy cell arrangement is disclosed using one capacitor per cell, and another embodiment uses two capacitors per cell with no dummy. The cells cooperate with a sense amplifier and timing signals so that they are self restoring.

Abstract: A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Later, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

Abstract: A memory cell includes an SRAM flip-flop cell having two nodes coupled to ferroelectric capacitors so that when the SRAM is powered down, the ferroelectric devices store data and upon power up, transfer the stored data to the SRAM cell. The ferroelectric devices can be bypassed during normal SRAM operations to reduce hysteresis fatigue.

Abstract: An improved semiconductor structure and the method for fabricating such is disclosed. The invention relates to the use of thick-oxide for improved field-shield isolation especially as applied to dynamic RAMS's and also to its integration into an improved CMOS process. The improved structure has increased isolation characteristics between adjacent memory cells and still allows for lessened spacing between cells. The corresponding process determines the spacing between cells through etching and eliminates several steps by utilizing one mask for several purposes including defining the active transistor areas and the first polysilicon layer and by extending the use of the first polysilicon layer for field-shield isolation between cells. Additional advantages are disclosed including a higher body effect in the isolation transistors, use of a nitride dielectric layer, and a higher, stable threshold voltage in the isolation transistors.