Patents by Inventor Saba Zare
Saba Zare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972785Abstract: A memory structure, i.e., magnetoresistive random access memory (MRAM) structure, is provided that includes a seeding area including at least a tunnel barrier seed layer located beneath a chemical templating layer that is wider than the magnetic tunnel junction (MTJ) structure that is located on the chemical templating layer. Redeposited metallic material is located on at least a sidewall of the tunnel barrier seed layer of the seeding area so as to shunt that area of the structure. The memory structure has reduced resistance with minimal tunnel magnetoresistance (TMR) loss penalty.Type: GrantFiled: November 15, 2021Date of Patent: April 30, 2024Assignee: International Business Machines CorporationInventors: Pouya Hashemi, Jonathan Zanhong Sun, Guohan Hu, Saba Zare
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Patent number: 11942126Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.Type: GrantFiled: May 26, 2021Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: Michael Rizzolo, Saba Zare, Virat Vasav Mehta, Eric Raymond Evarts
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Patent number: 11823724Abstract: A device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.Type: GrantFiled: October 26, 2021Date of Patent: November 21, 2023Assignee: International Business Machines CorporationInventors: Saba Zare, Dimitri Houssameddine, Karthik Yogendra, Heng Wu
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Publication number: 20230240148Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, a first metal line above the MTJ stack and a magnetoelectric material layer above the first metal line. A semiconductor device including an array of magnetic tunnel junction (MTJ) stacks, a first metal line connected physically and electrically to a top electrode of each MTJ stack in a row of the array of MTJ stacks and a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line. A method including forming an array of magnetic tunnel junction (MTJ) stacks, forming a first metal line above a row of the array of MTJ stacks, and forming a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line.Type: ApplicationFiled: January 25, 2022Publication date: July 27, 2023Inventors: Karthik Yogendra, Heng Wu, Saba Zare, Dimitri Houssameddine
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Publication number: 20230189656Abstract: A semiconductor device is provided. The semiconductor device includes a first electrode; an MRAM stack formed on the first electrode; a hardmask structure formed on the MRAM stack; a conductive etch stop layer formed around the hardmask structure; and a second electrode formed on the hardmask structure.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Inventors: SABA ZARE, MICHAEL RIZZOLO, THEODORUS E. STANDAERT, ALEXANDER REZNICEK
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Patent number: 11665974Abstract: An embodiment of the invention may include a magnetic random-access memory (MRAM) structure and method of making the structure. The MRAM structure may include a magnetic tunnel junction stack. The MRAM structure may include a magnetic liner located between the magnetic tunnel junction stack and a top contact, where the magnetic liner may be a ferromagnetic material. This may enable the magnetic liner to act as an independent variable to balance many of the magnetic parameters in the MTJ film stack in order to achieve zero magnetic field at the MTJ layer.Type: GrantFiled: January 27, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Michael Rizzolo, Saba Zare, Virat Vasav Mehta, Eric Raymond Evarts
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Patent number: 11664059Abstract: A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.Type: GrantFiled: June 2, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Dimitri Houssameddine, Saba Zare, Heng Wu, Karthik Yogendra
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Publication number: 20230154513Abstract: A memory structure, i.e., magnetoresistive random access memory (MRAM) structure, is provided that includes a seeding area including at least a tunnel barrier seed layer located beneath a chemical templating layer that is wider than the magnetic tunnel junction (MTJ) structure that is located on the chemical templating layer. Redeposited metallic material is located on at least a sidewall of the tunnel barrier seed layer of the seeding area so as to shunt that area of the structure. The memory structure has reduced resistance with minimal tunnel magnetoresistance (TMR) loss penalty.Type: ApplicationFiled: November 15, 2021Publication date: May 18, 2023Inventors: Pouya Hashemi, Jonathan Zanhong Sun, Guohan Hu, Saba Zare
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Publication number: 20230131445Abstract: A device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.Type: ApplicationFiled: October 26, 2021Publication date: April 27, 2023Inventors: Saba Zare, Dimitri Houssameddine, Karthik Yogendra, Heng Wu
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Publication number: 20230031478Abstract: A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Heng Wu, Dimitri Houssameddine, Saba Zare, Karthik Yogendra
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Patent number: 11569442Abstract: A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.Type: GrantFiled: June 17, 2020Date of Patent: January 31, 2023Assignee: International Business Machines CorporationInventors: Saba Zare, Michael Rizzolo, Mona A. Ebrish, Theodorus E. Standaert
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Publication number: 20220392504Abstract: A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Inventors: Dimitri Houssameddine, Saba Zare, Heng Wu, Karthik Yogendra
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Publication number: 20220383921Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Inventors: Michael Rizzolo, Saba Zare, Virat Vasav Mehta, Eric Raymond Evarts
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Publication number: 20220238794Abstract: An embodiment of the invention may include a magnetic random-access memory (MRAM) structure and method of making the structure. The MRAM structure may include a magnetic tunnel junction stack. The MRAM structure may include a magnetic liner located between the magnetic tunnel junction stack and a top contact, where the magnetic liner may be a ferromagnetic material. This may enable the magnetic liner to act as an independent variable to balance many of the magnetic parameters in the MTJ film stack in order to achieve zero magnetic field at the MTJ layer.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Michael Rizzolo, Saba Zare, Virat Vasav Mehta, Eric Raymond Evarts
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Publication number: 20220180911Abstract: An apparatus comprising a magnetic tunnel junction (MTJ), a diffusion barrier, wherein the MTJ is located on the diffusion barrier and a bottom contact that includes a magnetic field generating component, wherein the diffusion barrier is located on top of the bottom contact, wherein the magnetic field generated by the magnetic field generating component affects the stability of the MTJ.Type: ApplicationFiled: December 7, 2020Publication date: June 9, 2022Inventors: Saba Zare, Michael Rizzolo, Virat Vasav Mehta, Eric Raymond Evarts, Theodorus E. Standaert
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Publication number: 20210399212Abstract: A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.Type: ApplicationFiled: June 17, 2020Publication date: December 23, 2021Inventors: Saba Zare, Michael Rizzolo, Mona A. Ebrish, Theodorus E. Standaert
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Patent number: 11081643Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.Type: GrantFiled: January 21, 2020Date of Patent: August 3, 2021Assignee: International Business Machines CorporationInventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel C. Edelstein
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Publication number: 20210226120Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.Type: ApplicationFiled: January 21, 2020Publication date: July 22, 2021Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel C. Edelstein
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Publication number: 20210013400Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.Type: ApplicationFiled: July 9, 2019Publication date: January 14, 2021Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel Charles Edelstein
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Patent number: 10892404Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.Type: GrantFiled: July 9, 2019Date of Patent: January 12, 2021Assignee: International Business Machines CorporationInventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel Charles Edelstein