Patents by Inventor Saburou Iijima

Saburou Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6216236
    Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: April 10, 2001
    Assignees: Tokyo, Japan, Hitachi Process Computer Engineering, Inc.
    Inventors: Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Masayuki Tanji, Shigenori Kaneko, Koji Masui, Saburou Iijima, Nobuyasu Kanekawa, Shinichiro Kanekawa, Yoshiki Kobayashi, Hiroaki Fukumaru, Katsunori Tagiri
  • Patent number: 5901281
    Abstract: A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B).
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: May 4, 1999
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Masayuki Tanji, Shigenori Kaneko, Koji Masui, Saburou Iijima, Nobuyasu Kanekawa, Shinichiro Kanekawa, Yoshiki Kobayashi, Hiroaki Fukumaru, Katsunori Tagiri
  • Patent number: 5274808
    Abstract: A program replacing method is provided for an uninterruptible online computer system. The computer system includes an auxiliary storage unit for storing a program currently running in the computer system and another program to replace the current running program and a replacement request managing table for storing replacement requests and program IDs of such replacing programs. These programs include checkpoints pre-programmed at selected locations therein. At an optional checkpoint, the replacement request managing table is retrieved for checking whether or not the replacement is requested. If a replacement is requested, the new program is started according to the program ID and the current program is terminated.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: December 28, 1993
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Takeshi Miyao, Tomoaki Nakamura, Hiroshi Wataya, Saburou Iijima, Yasuo Sekine