Abstract: Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes a first set of SCRC switches and a second set of SCRC switches electrically connected between power supply lines and power reception lines. The first set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and the second operational mode. The second set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and electrically isolate the power supply lines from the power reception lines in the second operational mode. Activation of the first set of SCRC switches is staggered in time with activation of the second set of SCRC switches. The second set of SCRC switches is spaced among the first set of SCRC switches.

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode.

Abstract: When refresh activation signals (REFACT0 to REFACT3) are supplied, the internal memory cells in two or more memory banks (0 to 3) are refreshed. A refresh control circuit performs a first refresh control operation to activate a refresh operation in all of the memory banks when an auto refresh command is supplied, and performs a second refresh control operation to activate a refresh operation in a part of the memory banks when a self refresh command is supplied.

Abstract: When refresh activation signals (REFACT0 to REFACT3) are supplied, the internal memory cells in two or more memory banks (0 to 3) are refreshed. A refresh control circuit performs a first refresh control operation to activate a refresh operation in all of the memory banks when an auto refresh command is supplied, and performs a second refresh control operation to activate a refresh operation in a part of the memory banks when a self refresh command is supplied.

Abstract: A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from the storing unit. The selecting unit selects the input data. The selecting unit outputs the selected input data in parallel.

Abstract: A synchronous type semiconductor memory device includes a memory cell array in which memory cells are arranged in a matrix; a row address decoder which activates one of word lines in said memory cell array based on a row address in response to a word activation signal; a column decoder which activates one of bit line pairs in said memory cell array based on a column address; and a sense amplifier circuit which amplifies a voltage difference on the activated bit line pair in response to a sense amplifier activation signal. The synchronous type semiconductor memory device further includes a clock data storage section which stores clock data showing a frequency or period of an external clock signal; and a control section which generates the word activation signal based on a row address strobe signal, and generates the sense amplifier activation signal based on the clock data and the row address strobe signal in response to an internal clock signal synchronous with the external clock signal.

Abstract: A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied to the first node based on a delay control signal and generates first to n-th (n is an integer more than 1) internal clock signals. The first internal clock signal is outputted from the second node. Also, the internal clock signals other than the first internal clock signal are outputted from the delay circuit without passing through the second node, and lead the first internal clock signal in phase. The phase comparing circuit compares the original clock signal supplied from the first node and the first internal clock signal supplied from the second node, and outputs a phase difference of the original clock signal and the first internal clock signal. The delay control circuit outputs the delay control signal to the delay circuit based on the phase difference outputted from the phase comparing circuit.

Abstract: A synchronous type semiconductor memory device includes a memory cell array in which memory cells are arranged in a matrix; a row address decoder which activates one of word lines in said memory cell array based on a row address in response to a word activation signal; a column decoder which activates one of bit line pairs in said memory cell array based on a column address; and a sense amplifier circuit which amplifies a voltage difference on the activated bit line pair in response to a sense amplifier activation signal. The synchronous type semiconductor memory device further includes a clock data storage section which stores clock data showing a frequency or period of an external clock signal; and a control section which generates the word activation signal based on a row address strobe signal, and generates the sense amplifier activation signal based on the clock data and the row address strobe signal in response to an internal clock signal synchronous with the external clock signal.

Abstract: A semiconductor integrated circuit (50) having normal operation mode and a burn-in mode is provided. The semiconductor integrated circuit (50) can include a memory (14) and a logic circuit (9). The memory (14) may operate in response to input signals (input<5:0>) when in the burn-in mode while the logic circuit (9) may operate in response to control signals generated in response to one of the input signals (input<0>) having a predetermined value when the semiconductor integrated circuit (50) operates in the burn-in mode. The memory (14) may operate in response to memory control signals generated by the logic circuit (9) when the semiconductor integrated circuit (50) operates in the normal operation mode. The logic circuit (9) may generate the memory control signals in response to values provided by input signals (input<5:0>). In this way, the logic circuit (9) and memory (14) may be tested in the burn-in mode without providing additional inputs.

Abstract: A semiconductor device of the invention comprises: an external terminal; an internal circuit connected to the external terminal; a MOS transistor whose gate terminal or common terminal of the drain and source is connected to the external terminal; and a bonding pad for applying a predetermined voltage to a terminal which is not connected to the external terminal of the MOS transistor.

Abstract: A semiconductor integrated circuit (50) having normal operation mode and a burn-in mode is provided. The semiconductor integrated circuit (50) can include a memory (14) and a logic circuit (9). The memory (14) may operate in response to input signals (input<5:0>) when in the burn-in mode while the logic circuit (9) may operate in response to control signals generated in response to one of the input signals (input<0>) having a predetermined value when the semiconductor integrated circuit (50) operates in the burn-in mode. The memory (14) may operate in response to memory control signals generated by the logic circuit (9) when the semiconductor integrated circuit (50) operates in the normal operation mode. The logic circuit (9) may generate the memory control signals in response to values provided by input signals (input<5:0>). In this way, the logic circuit (9) and memory (14) may be tested in the burn-in mode without providing additional inputs.

Abstract: A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied to the first node based on a delay control signal and generates first to n-th (n is an integer more than 1) internal clock signals. The first internal clock signal is outputted from the second node. Also, the internal clock signals other than the first internal clock signal are outputted from the delay circuit without passing through the second node, and lead the first internal clock signal in phase. The phase comparing circuit compares the original clock signal supplied from the first node and the first internal clock signal supplied from the second node, and outputs a phase difference of the original clock signal and the first internal clock signal. The delay control circuit outputs the delay control signal to the delay circuit based on the phase difference outputted from the phase comparing circuit.

Abstract: A semiconductor memory device is used for outputting data synchronously with rise and fall phases of the reference clock, and includes: a first storage section for storing only the data for the rise-phases of the reference clock and successively outputting the data as read data; a second storage section for storing only the data for the fall-phases of the reference clock and successively outputting the data as read data; and an outputting circuit placed close to a terminal for outputting data externally, for receiving data forwarded from the first and second storage sections and outputting the received data successively according to the rise and fall edges of the reference clock. Of the first and second storage sections, the storage section that stores read data to be output first during a read operation is placed closer to the terminal than the other storage section.

Abstract: A semiconductor memory device is provided for simultaneously reading data of a plurality of bits from its memory cell region and outputting the data successively to an external environment, and includes: an external output section whose output state to the external environment is altered for one output logical level and not altered for another output logical level; a output level generation section for assigning a logical level corresponding to the content of bit-data to a bit freely selected out of the data, and assigning another output logical level to another bit; and a supply section for successively supplying the output logical levels, generated by the output level generation section to correspond with respective bits of the data, to the external output section.