Abstract: A method and apparatus for optimizing the yield of tested electronics devices is provided. A sample device is characterized to derive a specification for each device in the group. The sample size is chosen to provide reliable data and to minimize the effect of outlier devices on the characterization. After characterization, boundaries are set for the group of tested devices. Boundaries may be set based on voltages optimized for power consumption. The group of devices may be further subdivided into sub-groups based on the results of testing. The sub-groups are each assigned a unique code that reflects the results of the testing. This code is programmed into automated test equipment and is also stored in system software in order to ensure consistent values across the group of tested devices. The automated test equipment and system software are correlated using the same code to ensure higher test yield.

Abstract: A method and apparatus for an all-digital built in self test (BIST) of a phase locked loop includes a phase detector (PD), wherein the PD produces a digital signal describing a comparison between a reference signal and a feedback signal, and an all-digital programmable BIST coupled to the PD and a charge pump (CP). The BIST includes a digital counter to accumulate the digital signal, and a communication link, which provides the accumulated digital signal from the counter to automatic test equipment (ATE), which determines whether the PLL is operating correctly based on the accumulated digital signal. The method includes injecting signal pulses into the PLL to adjust a signal of the PLL, accumulating in a digital counter a digital signal that describes a comparison between the PLL feedback and reference signals, and determining whether the PLL is operating correctly based on the accumulated digital signal in the digital counter.

Abstract: A method and apparatus for optimizing the yield of tested electronics devices is provided. A sample device is characterized to derive a specification for each device in the group. The sample size is chosen to provide reliable data and to minimize the effect of outlier devices on the characterization. After characterization, boundaries are set for the group of tested devices. Boundaries may be set based on voltages optimized for power consumption. The group of devices may be further subdivided into sub-groups based on the results of testing. The sub-groups are each assigned a unique code that reflects the results of the testing. This code is programmed into automated test equipment and is also stored in system software in order to ensure consistent values across the group of tested devices. The automated test equipment and system software are correlated using the same code to ensure higher test yield.

Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

Abstract: An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal.

Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.