Abstract: An integrated circuit 2 includes logic circuitry 4 connected to virtual power rails 6, 8. These virtual power rails are connected via power control transistors 10, 16 to a power supply 14. A power controller 20 produces control signals which determines a number of the power control transistors 10, 16 which are in a conductive state and accordingly controls the virtual power rails to have an intermediate voltage level. The intermediate voltage level may be selected to hold the logic circuitry in a retention mode in which state is retained in the logic circuitry 4, but processing operations are not performed. When the functional mode is re-entered, all of the header and footer transistors 10, 16 may be switched to the conductive state.

Abstract: A monitoring circuit 14, 16, 18, 20, 22 for monitoring an operating parameter of an integrated circuit 2 comprises a ring oscillator circuit 80 comprising a plurality of serially connected inverting stages 82-1, 82-2, 82-3.At least one of the inverting stages 82-1, 82-2 comprises at least one leakage transistor 64-1, 64-2 which is configured to operate in a leakage mode in which substantially all current through the at least one leakage transistor is a leakage current, and a capacitive element 70-1 arranged to be charged or discharged in dependence on the leakage current. The ring oscillator circuit 80 thus generates an oscillating signal with an oscillation period dependent on a rate at which the capacitive element 70-1 is charged or discharged. The operating parameter controls a magnitude of the leakage current so that the oscillation period indicates the operating parameter.

Abstract: Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail.

Abstract: Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry.

Abstract: An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at an intermediate voltage level such that a reduced voltage difference is applied across the logic block. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks fully conductive and then the clock is restarted. The switch blocks which are modulated by controllers which use feedback control based upon the sensed virtual rail voltages (VVdd and Vgnd) while drawing their own power from the normal supply rails (Vdd and gnd).

Abstract: An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.

Abstract: Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element.

Abstract: Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry.

Abstract: A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.

Abstract: Power control circuitry for controlling connection of a voltage source to a switched power rail powering an associated circuit is provided. A plurality of switch blocks are connected in parallel between the switched power rail and the voltage source, each switch block being controlled by an enable signal provided by a switch controller. The switch controller performs a turn-on sequence providing a series of enable signal patterns to the switch blocks. The switch controller applies a time varying generation operation to at least one sequence stage of a predetermined turn-on sequence to produce a corresponding enable signal pattern for that sequence stage. When the turn-on sequence is later repeated, the enable signal pattern produced for at least one of the sequence stages differs from the enable signal pattern previously produced for that sequence stage.

Abstract: Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail.

Abstract: An integrated circuit 2 is provided with logic blocks 16 which draw their power from virtual supply rails 8, 10. These virtual supply rails 8, 10 are connected by switch blocks 12, 14 to main supply rails 4, 6. The switch blocks 12, 14 are subject to modulation to maintain the virtual supply rails 8, 10 at an intermediate voltage level such that a reduced voltage difference is applied across the logic block 16. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block 16 is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks 12, 14 fully conductive and then the clock is restarted.

Abstract: An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.