Patents by Inventor Sachin Shrivastava
Sachin Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11023948Abstract: The present invention provides an adaptive payment card system and process for providing a customer (referred to herein as a “cardholder”) with a payment card (referred to herein as an “adaptive” payment card) that is issued by an issuing financial institution (an “issuer”), and linked to a card entity (such as MasterCard), where the product associated with the adaptive payment card can be changed without modification to the corresponding payment card and without requiring issuance of a new payment card.Type: GrantFiled: May 15, 2018Date of Patent: June 1, 2021Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventors: Sachin Shrivastava, Ajitesh Pandey
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Patent number: 10984164Abstract: An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.Type: GrantFiled: October 23, 2019Date of Patent: April 20, 2021Assignee: Cadence Design Systems, Inc.Inventors: Ankur Chaplot, Yashu Gupta, Nikhil Garg, Sachin Shrivastava, Michaela Guiney, Sankalp Srivastava
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Patent number: 10417636Abstract: Described is a payment vehicle for use in initiating a transaction. The payment vehicle includes a body and an image applied to the body. The image includes encrypted data that is readable by an electronic reader to ascertain account details of a payment vehicle user, thereby to initiate the transaction. The image is also visually comparable to the user, or to information produced by the user, to confirm the user's identity.Type: GrantFiled: December 20, 2016Date of Patent: September 17, 2019Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventors: Ravi Pareek, Arunmurthy Gurunathan, Sachin Shrivastava
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Patent number: 10296703Abstract: The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.Type: GrantFiled: September 20, 2017Date of Patent: May 21, 2019Assignee: Cadence Design Systems, Inc.Inventors: Pardeep Juneja, Jean-Marc Bourguet, Joyjeet Bose, Sachin Shrivastava, Yashu Gupta, Ankur Chaplot
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Patent number: 10192021Abstract: Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.Type: GrantFiled: February 21, 2017Date of Patent: January 29, 2019Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Satish Raj, Ying-Hui Wang, Joyjeet Bose, Sachin Shrivastava
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Publication number: 20180374139Abstract: The present invention provides an adaptive payment card system and process for providing a customer (referred to herein as a “cardholder”) with a payment card (referred to herein as an “adaptive” payment card) that is issued by an issuing financial institution (an “issuer”), and linked to a card entity (such as MasterCard), where the product associated with the adaptive payment card can be changed without modification to the corresponding payment card and without requiring issuance of a new payment card.Type: ApplicationFiled: May 15, 2018Publication date: December 27, 2018Inventors: Sachin Shrivastava, Ajitesh Pandey
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Publication number: 20170286949Abstract: A computerised method for performing a transaction is disclosed. The method comprises: generating, by a merchant billing machine at a merchant location, transaction data comprising a transaction cost and identifying, via the merchant billing machine, a customer digital wallet and/or number for a customer mobile device. The merchant billing machine then communicates the transaction data and identification of a merchant digital wallet to the customer digital wallet and/or customer mobile device. A digital wallet server receives, upon authorisation of the transaction via the customer mobile device, the transaction data and merchant digital wallet identification along with details of a customer payment vehicle and transfers the transaction cost from the customer payment vehicle to the merchant digital wallet.Type: ApplicationFiled: March 28, 2017Publication date: October 5, 2017Inventors: Arunmurthy Gurunathan, Ravi Pareek, Sachin Shrivastava
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Publication number: 20170206527Abstract: Described is a payment vehicle for use in initiating a transaction. The payment vehicle includes a body and an image applied to the body. The image includes encrypted data that is readable by an electronic reader to ascertain account details of a payment vehicle user, thereby to initiate the transaction. The image is also visually comparable to the user, or to information produced by the user, to confirm the user's identity.Type: ApplicationFiled: December 20, 2016Publication date: July 20, 2017Applicant: Mastercard International IncorporatedInventors: Ravi PAREEK, Arunmurthy GURUNATHAN, Sachin SHRIVASTAVA
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Patent number: 8813006Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.Type: GrantFiled: March 26, 2008Date of Patent: August 19, 2014Assignee: Cadence Design Systems, Inc.Inventors: Harindranath Parameswaran, Sachin Shrivastava
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Patent number: 8762908Abstract: In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.Type: GrantFiled: June 27, 2010Date of Patent: June 24, 2014Assignee: Cadence Design Systems, Inc.Inventors: Hongliang Chang, Vassilios Gerousis, Sireesha Molakalapalli, Sachin Shrivastava
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Patent number: 8612199Abstract: Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.Type: GrantFiled: December 20, 2007Date of Patent: December 17, 2013Assignee: Cadence Design Systems, Inc.Inventors: Sachin Shrivastava, Harindranath Parameswaran
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Patent number: 8336010Abstract: In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.Type: GrantFiled: June 27, 2010Date of Patent: December 18, 2012Assignee: Cadence Design Systems, Inc.Inventors: Hongliang Chang, Vassilios Gerousis, Sireesha Molakalapalli, Sachin Shrivastava
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Patent number: 8086978Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.Type: GrantFiled: June 20, 2008Date of Patent: December 27, 2011Assignee: Cadence Design Systems, Inc.Inventors: Lizheng Zhang, Parveen Khurana, Vassilios Gerousis, Hongliang Chang, Sachin Shrivastava
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Patent number: 8086983Abstract: A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.Type: GrantFiled: September 30, 2008Date of Patent: December 27, 2011Assignee: Cadence Design Systems, Inc.Inventors: Sachin Shrivastava, Harindranath Parameswaran
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Publication number: 20100083202Abstract: A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Sachin Shrivastava, Harindranath Parameswaran
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Publication number: 20090319969Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Inventors: Lizheng Zhang, Parveen Khurana, Vassilios Gerousis, Hongliang Chang, Sachin Shrivastava
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Publication number: 20090164194Abstract: Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Inventors: Sachin Shrivastava, Harindranath Parameswaran