Patents by Inventor Sachiro Kayanuma

Sachiro Kayanuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabrication of semiconductor device having polycrystalline silicon and metal silicides
    Patent number: 5397729
    Abstract: A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: March 14, 1995
    Assignee: Asahi Kasei Microsystems Co., Ltd.
    Inventors: Sachiro Kayanuma, Koji Iki