Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: A method for forming three gate oxide films having different thicknesses in first through third circuit areas, respectively. The method includes the consecutive steps of forming a first gate oxide film having a largest thickness in all the areas, removing the first gate oxide film and forming a second gate oxide film having a second largest thickness in the second circuit area, and removing the first gate oxide and forming a third gate oxide film having a smallest thickness in the third circuit area. The resultant gate oxide films have accurate thicknesses.

Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: An objective of this invention is to provide a process for manufacturing a shared contact without protrusion toward an adjacent gate electrode and an improved shared contact. This invention allows a shared contact without protrusion from the gate electrode to be prepared by removing a gate electrode which is in contact with a dopant diffusion layer but is not used as a transistor element and forming a shared contact in the area. As a result, a cell size is larger in an SRAM according to this invention than in that according to the prior art.

Abstract: In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

Abstract: In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

Abstract: In a method of manufacturing a two-type power supply voltage compatible CMOS semiconductor, the number of photolithography steps that aim at forming an LDD, a pocket, and a source/drain region is reduced so that time and cost are economized. For this purpose, an LDD structure of a low power supply voltage compatible portion and an LDD structure of a high power supply voltage compatible portion are formed at once and not separately.

Abstract: A method of fabricating a CMOS semiconductor device is provided, which decreases the number of necessary photolithography processes for forming the LDD and pocket structures. A first pair of doped regions of a first conductivity type are formed in a first section of a semiconductor substrate and a second pair of doped regions of the first conductivity type are formed in a second section thereof. Then, a third pair of doped regions of a second conductivity type are formed in the first pair of doped regions and a fourth pair of doped regions of the second conductivity type are formed in the second pair of doped regions. Thereafter, an impurity of the second conductivity type is selectively ion-implanted into the first section while covering the second section with a mask, thereby forming a fifth pair of doped regions of the second conductivity type from the first pair of remaining doped regions.

Abstract: In order to suppress a reverse short-channel effect, a plurality of dummy gates, wherein gate electrodes are respectively to be formed, are formed in selective regions on the substrate. Further, the regions wherein first conductive type elements are to be formed are masked. Thereafter, a first conductive type well by ion planting a first conductive type impurity is formed. Further, a second conductive type source and drain region is formed by ion planting a second conductive type impurity. The resist covering the regions, wherein the first conductive type elements are to be formed, are removed. Following this, regions wherein second conductive type elements are to be formed, are masked by a resist. Further, a second conductive type well is formed by ion planting a second conductive type impurity. A first conductive type source and drain region is formed by ion planting a first conductive type impurity.

Abstract: A CMOS device includes a first conductive type channel MOSFET having first side-wall spacers on side surfaces and having a source and drain region of an LDD structure, and a second conductive type channel MOSFET having second side-wall spacers on side surfaces and having a source and drain region of a single drain structure, wherein a width of the first side-wall spacers is larger than that of the second side-wall spacers, restraining the short channel effect and hot carrier effect as well.

Abstract: A method for ion-implantation of a first conductivity impurity into a substrate of the same conductivity type to form pocket regions at positions in the inside edge portion of source/drain regions of a second conductivity type in a MOSFET having gate electrodes with side wall silicon oxide films. Semiconductor epitaxial layers are formed on the source/drain regions of a high selectivity to the side wall oxide films so that the epitaxial layers have facets which face to the side wall oxide films and the facets are almost linearly sloped down to bottom portions of the side wall oxide films. The first conductivity type impurity is implanted into the substrate at its limited positions in the vicinity of the inside edge portion of the source/drain regions by using the epitaxial layers with the facets and the side wall oxide films as masks in an oblique direction tilted by a tilting angle .theta. from the normal of a surface of the substrate, wherein the angle .theta. satisfies an equation represented by .theta..