Patents by Inventor Sadami Takeoka
Sadami Takeoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7613972Abstract: A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.Type: GrantFiled: October 25, 2006Date of Patent: November 3, 2009Assignee: Panasonic CorporationInventors: Sadami Takeoka, Shinichi Yoshimura
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Patent number: 7610533Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.Type: GrantFiled: November 4, 2005Date of Patent: October 27, 2009Assignee: Panasonic CorporationInventors: Takashi Ishimura, Sadami Takeoka
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Patent number: 7590908Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.Type: GrantFiled: February 23, 2009Date of Patent: September 15, 2009Assignee: Panasonic CorporationInventors: Takashi Ishimura, Sadami Takeoka
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Publication number: 20090164860Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.Type: ApplicationFiled: February 23, 2009Publication date: June 25, 2009Applicant: PANASONIC CORPORATIONInventors: Takashi Ishimura, Sadami Takeoka
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Publication number: 20090106721Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.Type: ApplicationFiled: December 15, 2008Publication date: April 23, 2009Applicant: PANASONIC CORPORATIONInventors: Sadami TAKEOKA, Takahiro ICHINOMIYA, Akira MOTOHARA
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Patent number: 7512853Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.Type: GrantFiled: November 4, 2005Date of Patent: March 31, 2009Assignee: Panasonic CorporationInventors: Takashi Ishimura, Sadami Takeoka
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Patent number: 7475378Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.Type: GrantFiled: March 15, 2005Date of Patent: January 6, 2009Assignee: Panasonic CorporationInventor: Sadami Takeoka
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Patent number: 7348595Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.Type: GrantFiled: April 21, 2004Date of Patent: March 25, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
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Patent number: 7302658Abstract: In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a “design delay value” on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides “methods of evaluating the quality of test sequences for delay faults” capable of evaluating the quality of the “delay fault test sequences” with more accuracy.Type: GrantFiled: January 28, 2004Date of Patent: November 27, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta
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Publication number: 20070250284Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.Type: ApplicationFiled: February 28, 2007Publication date: October 25, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura, Takashi Ishimura
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Publication number: 20070113131Abstract: A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.Type: ApplicationFiled: October 25, 2006Publication date: May 17, 2007Inventors: Sadami Takeoka, Shinichi Yoshimura
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Publication number: 20070106965Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuyasu Ohta, Sadami Takeoka
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Patent number: 7203913Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.Type: GrantFiled: October 28, 2002Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuyasu Ohta, Sadami Takeoka
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Patent number: 7197725Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.Type: GrantFiled: July 2, 2002Date of Patent: March 27, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura, Takashi Ishimura
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Publication number: 20070038908Abstract: Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of the design data and, after the code analysis, the resulting design data is stored by a database storage unit in a storage device. A test point deletion unit receives the test mode specified from the outside and deletes data on an unnecessary test point from the design data stored in the storage device. The design data which does not include the unnecessary test point is outputted from a data output unit. Accordingly, even when the test mode is changed, there is no need to calculate the test efficiency again in response to each change or add the step of inserting a new test point.Type: ApplicationFiled: March 20, 2006Publication date: February 15, 2007Inventors: Yoko Hirano, Katsuya Fujimura, Aya Mototani, Sadami Takeoka
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Patent number: 7171600Abstract: An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.Type: GrantFiled: April 21, 2004Date of Patent: January 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
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Patent number: 7159143Abstract: All untestable delay faults are hardly calculated. Thus, when the fault coverage of an test sequence for a delay fault is calculated, the fault coverage is not calculated without excluding the number of untestable faults. Accordingly the fault coverage does not correctly represent a test quality. The delay faults are partly selected to analyze how many untestable delay faults exist among the selected delay faults. Thus, the, number of untestable delay faults included all the delay faults are estimated. Thus, a method for evaluating a delay fault test quality for calculating the fault coverage that correctly represents the test quality by using this value is provided.Type: GrantFiled: January 30, 2004Date of Patent: January 2, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Seiji Kajihara
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Publication number: 20060174176Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.Type: ApplicationFiled: November 4, 2005Publication date: August 3, 2006Inventors: Takashi Ishimura, Sadami Takeoka
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Patent number: 7032196Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.Type: GrantFiled: April 21, 2004Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
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Patent number: 7017135Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.Type: GrantFiled: April 30, 2001Date of Patent: March 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Sadami Takeoka, Takahiro Ichinomiya, Akira Motohara