Abstract: An apparatus and method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having a symmetrical interconnect system for attaching one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped poles can be arranged on the same side of a chip in an opposing fashion, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads.

Abstract: A method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having asymmetrical interconnect system for one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped holes can be arranged on the same side of the ship in an opposing action, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chips surfaces, such that antenna substrates can be attached to both the top and bottom of the chip to form a product “sandwich”, whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Abstract: Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.

Abstract: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Abstract: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Abstract: An apparatus and method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having a symmetrical interconnect system for attaching one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped poles can be arranged on the same side of a chip in an opposing fashion, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chip surfaces, such that antenna substrates can attach to both the top and bottom of the chip to form a product “sandwich,” whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Abstract: A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages are disclosed. The described lead frames are generally arranged such that each device area has a plurality of contacts but no die attach pad. With this arrangement, the back surface of the die is exposed and coplanar with the exposed bottom surface of the contacts. A casing material (typically plastic) holds the contacts and die in place. In one aspect of the invention, the back surface of the die is metallized. The metallization forms a good attachment surface for the package and serves as a good thermal path to transfer heat away from the die. In another aspect, at least some of the contacts have a top surface, a shelf, and a bottom surface. The die is wire bonded (or otherwise electrically connected) to the shelf portions of the contacts. The described package is quite versatile.

Abstract: A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.