Abstract: A cache control circuit in a cache memory unit having a cache memory in cooperation with an address conversion unit for converting a logical address into a physical address, a main memory, and a central processing unit. The central processing unit issues a control signal comprising a write/read request together with a logical address. The address conversion unit converts the logical address into the physical address which is applied to the cache memory unit. When the address conversion unit does not have a physical address corresponding to the logical address, the address conversion unit delivers a mismatch signal to the central processing unit and the cache control circuit to inform them of invalidation of the issued read/write request. The cache memory unit decides whether or not the physical address received is valid in the cache memory unit and produces a hit signal when it is valid.

Abstract: In a bus arbitration network comprising a common bus network, a plurality of bus masters, and a bus arbiter, each of the bus masters supplies others of the bus masters through the common bus network with either a normal bus request signal or a particular bus request signal having a high priority in comparison with the normal bus request signal. A bus request signal is also supplied from each bus master to the bus arbiter which delivers a bus acknowledgement signal to each bus master. Supply of either the normal or the particular bus request signal and the bus request signal is prohibited by each bus master when each bus master is supplied with the particular bus request signal from the other bus masters. A lock signal may be delivered from each bus master to the other bus masters through the common bus network to continuously use the common bus network.