Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.