Abstract: Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths.

Abstract: In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number.

Abstract: Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths.

Abstract: An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.

Abstract: In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number.

Abstract: A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1) generating a shift count indicating the number of bit positions, if any, a mantissa of an unnormalized floating-point number is to be left shifted to normalize the unnormalized floating-point number, (2) generating a right shift indicator indicating the number of bit positions, if any, the mantissa is to be right shifted to normalize the unnormalized floating-point number, (3) incrementing the value of an exponent of the unnormalized floating-point number, (4) concurrently with the incrementing step, complementing a plurality of bits of the shift count and (5) adding the exponent, the shift count and the right shift indicator to generate an exponent of a normalized floating-point number. The method and circuit may be implemented in a floating-point adder.

Abstract: An arithmetic unit wherein a plurality of electrical signals corresponding to the mantissa is shifted and a bit signal corresponding to the sticky bit is calculated simultaneously with the calculation of the shift count. Initially, a serial approach to mantissa shifting and sticky bit calculation is employed. A parallel approach to matissa shifting and sticky bit calculation is adopted when all shift count bits are available. In one embodiment of the present invention, an exclusive OR gate is used to calculate the difference between the least significant bits of the first and second exponents. A shifter/sticky bit calculator immediately acts upon the output of the exclusive OR gate and begins shifting the mantissa and calculating the guard, round, and sticky bits. The more significant bits of the shift count are progressively generated thereafter, and the guard, round and sticky bits are calculated and the mantissa is shifted as the shift count bits become available.